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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd161608 176-rgb x 220-dot 1-chip driver ic for 262,144-color tft-lcd display data sheet document no. s17594ej2v0ds00 (2nd edition) date published june 2006 ns cp(k) printed in japan 2004, 2005 the mark data sheet s17594ej2v0ds 2 pd161608 1. block diagram vlcd63 220ch-gate driver display timing control gamma adjusting circuit gray-scale voltage generator 528ch-source driver d/a circuit line latch circuit shift registers serial peripheral i/f (spi) control register decoding 18-bits rgb i/f level shifter control power regulator bulit-in power supply circuit exvr vcix2 vci2 64 3168 3168 3168 18 vgh vgl vci vcoml vcomr vcom rvdd enable dotclk vsync hsync resetb regvdd g219 s527 s526 g218 g2 s2 s1 s0 g1 g0 shut tb cm rl rev bgr spid csb sck sdi sdo rr [5:0] gg [5:0] bb [5:0] v ddio v dd v ss cad tmb vcomh cxp cxn cyp cyn c1p c1n c2p c2n c3p c3n data sheet s17594ej2v0ds 3 pd161608 2. pad configuration 1400 m 1 277 pad size: 35 m x 80 m, the number of pad: 17 20960 m +y +x bump side up 279 278 1043 input pad pitch&size (pad no.1-277) (pad no.280-1041) (pad no.278, 279, 280-1041, 1042, 1043) (pad no.278, 279, 1042, 1043) 1042 75 m 51 m 24 m 118 m 130 m 53 m 53 m 53 m 66 m 27 m 27 m 27 m 54 m 24 m 50 m 100 m 100 m 30 m pad a output pad pitch&size pad b, c pad b pad c nc nc nc g0 g4 g4 g2 gtestl 110 m 50 m 25 m 17 1 2 remark nc: no connection data sheet s17594ej2v0ds 4 pd161608 table 2 ? 1. pad dimensions size items pad name x y unit chip size (with scribe lane: 100 m) ? 20960 1400 chip thickness ? 400 pad pitch 1 to 277 75 278, 279, 1042, 1043 53 280 to 1041 27 bump pad size 1 to 277 51 118 278, 279, 1042, 1043 50 100 280 to 1041 24 100 bump height ? 15 m data sheet s17594ej2v0ds 5 pd161608 figure 2 ? 1. alignment mark configurations (unit: m) 25 25 25 25 25 25 center ( ? 10368, 310) center ( ? 10347, ? 340) center (10368, 310) center (10347, ? 340) 25 25 25 25 25 25 15 10 25 25 25 37.5 37.5 25 25 25 25 25 25 10 15 data sheet s17594ej2v0ds 6 pd161608 table 2 ? 2. pad coordinate (1/5) pad no. name x y pad no. name x y pad no. name x y pad no. name x y 1 nc -10350 -520 61 cxp -5850 -520 121 nc -1350 -520 181 rev 3150 -520 2 nc -10275 -520 62 cxp -5775 -520 122 vss -1275 -520 182 vddio 3225 -520 3 vcom -10200 -520 63 cxp -5700 -520 123 vss -1200 -520 183 bgr 3300 -520 4 vcom -10125 -520 64 vcoml -5625 -520 124 vss -1125 -520 184 bgr 3375 -520 5 vcom -10050 -520 65 vcoml -5550 -520 125 vss -1050 -520 185 vss 3450 -520 6 dummy -9975 -520 66 vcoml -5475 -520 126 tmb -975 -520 186 tb 3525 -520 7 dummy -9900 -520 67 vcomh -5400 -520 127 vss -900 -520 187 tb 3600 -520 8 cdum0 -9825 -520 68 vcomh -5325 -520 128 vss -825 -520 188 vddio 3675 -520 9 cdum0 -9750 -520 69 vcomh -5250 -520 129 vss -750 -520 189 rl 3750 -520 10 cdum0 -9675 -520 70 vgl -5175 -520 130 vss -675 -520 190 rl 3825 -520 11 cdum1 -9600 -520 71 vgl -5100 -520 131 nc -600 -520 191 vss 3900 -520 12 cdum1 -9525 -520 72 vgl -5025 -520 132 vss -525 -520 192 shut 3975 -520 13 cdum1 -9450 -520 73 vgh -4950 -520 133 vss -450 -520 193 shut 4050 -520 14 nc -9375 -520 74 vgh -4875 -520 134 vss -375 -520 194 shut 4125 -520 15 nc -9300 -520 75 vgh -4800 -520 135 vss -300 -520 195 dotclk 4200 -520 16 nc -9225 -520 76 vcoml -4725 -520 136 vss -225 -520 196 dotclk 4275 -520 17 nc -9150 -520 77 vcoml -4650 -520 137 nc -150 -520 197 dotclk 4350 -520 18 nc -9075 -520 78 vcoml -4575 -520 138 vci -75 -520 198 hsync 4425 -520 19 nc -9000 -520 79 vci2 -4500 -520 139 vci 0 -520 199 hsync 4500 -520 20 nc -8925 -520 80 vci2 -4425 -520 140 vci 75 -520 200 hsync 4575 -520 21 vss -8850 -520 81 vci2 -4350 -520 141 vci 150 -520 201 vsync 4650 -520 22 nc -8775 -520 82 nc -4275 -520 142 vci 225 -520 202 vsync 4725 -520 23 nc -8700 -520 83 vcix2 -4200 -520 143 vci 300 -520 203 vsync 4800 -520 24 nc -8625 -520 84 vcix2 -4125 -520 144 vci 375 -520 204 enable 4875 -520 25 nc -8550 -520 85 vcix2 -4050 -520 145 vci 450 -520 205 enable 4950 -520 26 nc -8475 -520 86 vcix2 -3975 -520 146 vci 525 -520 206 enable 5025 -520 27 nc -8400 -520 87 vcix2 -3900 -520 147 vci 600 -520 207 vddio 5100 -520 28 c3n -8325 -520 88 vcix2 -3825 -520 148 vdd 675 -520 208 rr5 5175 -520 29 c3n -8250 -520 89 vcix2 -3750 -520 149 vdd 750 -520 209 rr5 5250 -520 30 c3n -8175 -520 90 vlcd63 -3675 -520 150 vdd 825 -520 210 rr5 5325 -520 31 c3p -8100 -520 91 vlcd63 -3600 -520 151 vdd 900 -520 211 rr4 5400 -520 32 c3p -8025 -520 92 vlcd63 -3525 -520 152 nc 975 -520 212 rr4 5475 -520 33 c3p -7950 -520 93 vlcd63 -3450 -520 153 vddio 1050 -520 213 rr4 5550 -520 34 c2n -7875 -520 94 vlcd63 -3375 -520 154 vddio 1125 -520 214 rr3 5625 -520 35 c2n -7800 -520 95 vlcd63 -3300 -520 155 sdo 1200 -520 215 rr3 5700 -520 36 c2n -7725 -520 96 vlcd63 -3225 -520 156 sdo 1275 -520 216 rr3 5775 -520 37 c2p -7650 -520 97 vlcd63 -3150 -520 157 sdi 1350 -520 217 rr2 5850 -520 38 c2p -7575 -520 98 testa -3075 -520 158 sdi 1425 -520 218 rr2 5925 -520 39 c2p -7500 -520 99 vcomh -3000 -520 159 sck 1500 -520 219 rr2 6000 -520 40 testc -7425 -520 100 vcomh -2925 -520 160 sck 1575 -520 220 rr1 6075 -520 41 testb -7350 -520 101 vcomh -2850 -520 161 csb 1650 -520 221 rr1 6150 -520 42 c1n -7275 -520 102 nc -2775 -520 162 csb 1725 -520 222 rr1 6225 -520 43 c1n -7200 -520 103 rvdd -2700 -520 163 csb 1800 -520 223 rr0 6300 -520 44 c1n -7125 -520 104 rvdd -2625 -520 164 resb 1875 -520 224 rr0 6375 -520 45 c1p -7050 -520 105 rvdd -2550 -520 165 resb 1950 -520 225 rr0 6450 -520 46 c1p -6975 -520 106 rvdd -2475 -520 166 resb 2025 -520 226 gg5 6525 -520 47 c1p -6900 -520 107 rvdd -2400 -520 167 vss 2100 -520 227 gg5 6600 -520 48 vss -6825 -520 108 rvdd -2325 -520 168 testin1 2175 -520 228 gg5 6675 -520 49 vss -6750 -520 109 exvr -2250 -520 169 testin2 2250 -520 229 gg4 6750 -520 50 cyn -6675 -520 110 vcomr -2175 -520 170 vddio 2325 -520 230 gg4 6825 -520 51 cyn -6600 -520 111 vcomr -2100 -520 171 spid 2400 -520 231 gg4 6900 -520 52 cyn -6525 -520 112 nc -2025 -520 172 spid 2475 -520 232 gg3 6975 -520 53 cyp -6450 -520 113 vss -1950 -520 173 vss 2550 -520 233 gg3 7050 -520 54 cyp -6375 -520 114 vss -1875 -520 174 regvdd 2625 -520 234 gg3 7125 -520 55 cyp -6300 -520 115 vss -1800 -520 175 regvdd 2700 -520 235 gg2 7200 -520 56 vci -6225 -520 116 vss -1725 -520 176 vddio 2775 -520 236 gg2 7275 -520 57 vdd -6150 -520 117 vss -1650 -520 177 cad 2850 -520 237 gg2 7350 -520 58 cxn -6075 -520 118 vss -1575 -520 178 cad 2925 -520 238 gg1 7425 -520 59 cxn -6000 -520 119 vss -1500 -520 179 vss 3000 -520 239 gg1 7500 -520 60 cxn -5925 -520 120 vss -1425 -520 180 rev 3075 -520 240 gg1 7575 -520 data sheet s17594ej2v0ds 7 pd161608 table 2 ? 2. pad coordinate (2/5) pad no. name x y pad no. name x y pad no. name x y pad no. name x y 241 gg0 7650 -520 301 g43 9706.5 444 361 g159 8086.5 444 421 s501 6466.5 444 242 gg0 7725 -520 302 g45 9679.5 574 362 g161 8059.5 574 422 s500 6439.5 574 243 gg0 7800 -520 303 g47 9652.5 444 363 g163 8032.5 444 423 s499 6412.5 444 244 bb0 7875 -520 304 g49 9625.5 574 364 g165 8005.5 574 424 s498 6385.5 574 245 bb0 7950 -520 305 g51 9598.5 444 365 g167 7978.5 444 425 s497 6358.5 444 246 bb0 8025 -520 306 g53 9571.5 574 366 g169 7951.5 574 426 s496 6331.5 574 247 bb1 8100 -520 307 g55 9544.5 444 367 g171 7924.5 444 427 s495 6304.5 444 248 bb1 8175 -520 308 g57 9517.5 574 368 g173 7897.5 574 428 s494 6277.5 574 249 bb1 8250 -520 309 g59 9490.5 444 369 g175 7870.5 444 429 s493 6250.5 444 250 bb2 8325 -520 310 g61 9463.5 574 370 g177 7843.5 574 430 s492 6223.5 574 251 bb2 8400 -520 311 g63 9436.5 444 371 g179 7816.5 444 431 s491 6196.5 444 252 bb2 8475 -520 312 g65 9409.5 574 372 g181 7789.5 574 432 s490 6169.5 574 253 bb3 8550 -520 313 g67 9382.5 444 373 g183 7762.5 444 433 s489 6142.5 444 254 bb3 8625 -520 314 g69 9355.5 574 374 g185 7735.5 574 434 s488 6115.5 574 255 bb3 8700 -520 315 g71 9328.5 444 375 g187 7708.5 444 435 s487 6088.5 444 256 bb4 8775 -520 316 g73 9301.5 574 376 g189 7681.5 574 436 s486 6061.5 574 257 bb4 8850 -520 317 g75 9274.5 444 377 g191 7654.5 444 437 s485 6034.5 444 258 bb4 8925 -520 318 g77 9247.5 574 378 g193 7627.5 574 438 s484 6007.5 574 259 bb5 9000 -520 319 g79 9220.5 444 379 g195 7600.5 444 439 s483 5980.5 444 260 bb5 9075 -520 320 g81 9193.5 574 380 g197 7573.5 574 440 s482 5953.5 574 261 bb5 9150 -520 321 g83 9166.5 444 381 g199 7546.5 444 441 s481 5926.5 444 262 cm 9225 -520 322 g85 9139.5 574 382 g201 7519.5 574 442 s480 5899.5 574 263 cm 9300 -520 323 g87 9112.5 444 383 g203 7492.5 444 443 s479 5872.5 444 264 cm 9375 -520 324 g89 9085.5 574 384 g205 7465.5 574 444 s478 5845.5 574 265 testin3 9450 -520 325 g91 9058.5 444 385 g207 7438.5 444 445 s477 5818.5 444 266 testin4 9525 -520 326 g93 9031.5 574 386 g209 7411.5 574 446 s476 5791.5 574 267 testin5 9600 -520 327 g95 9004.5 444 387 g211 7384.5 444 447 s475 5764.5 444 268 testout 9675 -520 328 g97 8977.5 574 388 g213 7357.5 574 448 s474 5737.5 574 269 testout 9750 -520 329 g99 8950.5 444 389 g215 7330.5 444 449 s473 5710.5 444 270 testout 9825 -520 330 g101 8923.5 574 390 g217 7303.5 574 450 s472 5683.5 574 271 dummy 9900 -520 331 g103 8896.5 444 391 g219 7276.5 444 451 s471 5656.5 444 272 dummy 9975 -520 332 g105 8869.5 574 392 gtestr 7249.5 574 452 s470 5629.5 574 273 vcom 10050 -520 333 g107 8842.5 444 393 nc 7222.5 444 453 s469 5602.5 444 274 vcom 10125 -520 334 g109 8815.5 574 394 nc 7195.5 574 454 s468 5575.5 574 275 vcom 10200 -520 335 g111 8788.5 444 395 s527 7168.5 444 455 s467 5548.5 444 276 nc 10275 -520 336 nc 8761.5 574 396 s526 7141.5 574 456 s466 5521.5 574 277 nc 10350 -520 337 nc 8734.5 444 397 s525 7114.5 444 457 s465 5494.5 444 278 nc 10379.5 574 338 g113 8707.5 574 398 s524 7087.5 574 458 s464 5467.5 574 279 nc 10326.5 444 339 g115 8680.5 444 399 s523 7060.5 444 459 s463 5440.5 444 280 g1 10273.5 574 340 g117 8653.5 574 400 s522 7033.5 574 460 s462 5413.5 574 281 g3 10246.5 444 341 g119 8626.5 444 401 s521 7006.5 444 461 s461 5386.5 444 282 g5 10219.5 574 342 g121 8599.5 574 402 s520 6979.5 574 462 s460 5359.5 574 283 g7 10192.5 444 343 g123 8572.5 444 403 s519 6952.5 444 463 s459 5332.5 444 284 g9 10165.5 574 344 g125 8545.5 574 404 s518 6925.5 574 464 s458 5305.5 574 285 g11 10138.5 444 345 g127 8518.5 444 405 s517 6898.5 444 465 s457 5278.5 444 286 g13 10111.5 574 346 g129 8491.5 574 406 s516 6871.5 574 466 s456 5251.5 574 287 g15 10084.5 444 347 g131 8464.5 444 407 s515 6844.5 444 467 s455 5224.5 444 288 g17 10057.5 574 348 g133 8437.5 574 408 s514 6817.5 574 468 s454 5197.5 574 289 g19 10030.5 444 349 g135 8410.5 444 409 s513 6790.5 444 469 s453 5170.5 444 290 g21 10003.5 574 350 g137 8383.5 574 410 s512 6763.5 574 470 s452 5143.5 574 291 g23 9976.5 444 351 g139 8356.5 444 411 s511 6736.5 444 471 s451 5116.5 444 292 g25 9949.5 574 352 g141 8329.5 574 412 s510 6709.5 574 472 s450 5089.5 574 293 g27 9922.5 444 353 g143 8302.5 444 413 s509 6682.5 444 473 s449 5062.5 444 294 g29 9895.5 574 354 g145 8275.5 574 414 s508 6655.5 574 474 s448 5035.5 574 295 g31 9868.5 444 355 g147 8248.5 444 415 s507 6628.5 444 475 s447 5008.5 444 296 g33 9841.5 574 356 g149 8221.5 574 416 s506 6601.5 574 476 s446 4981.5 574 297 g35 9814.5 444 357 g151 8194.5 444 417 s505 6574.5 444 477 s445 4954.5 444 298 g37 9787.5 574 358 g153 8167.5 574 418 s504 6547.5 574 478 s444 4927.5 574 299 g39 9760.5 444 359 g155 8140.5 444 419 s503 6520.5 444 479 s443 4900.5 444 300 g41 9733.5 574 360 g157 8113.5 574 420 s502 6493.5 574 480 s442 4873.5 574 data sheet s17594ej2v0ds 8 pd161608 table 2 ? 2. pad coordinate (3/5) pad no. name x y pad no. name x y pad no. name x y pad no. name x y 481 s441 4846.5 444 541 s381 3226.5 444 601 s321 1606.5 444 661 nc -13.5 444 482 s440 4819.5 574 542 s380 3199.5 574 602 s320 1579.5 574 662 nc -40.5 574 483 s439 4792.5 444 543 s379 3172.5 444 603 s319 1552.5 444 663 s263 -67.5 444 484 s438 4765.5 574 544 s378 3145.5 574 604 s318 1525.5 574 664 s262 -94.5 574 485 s437 4738.5 444 545 s377 3118.5 444 605 s317 1498.5 444 665 s261 -121.5 444 486 s436 4711.5 574 546 s376 3091.5 574 606 s316 1471.5 574 666 s260 -148.5 574 487 s435 4684.5 444 547 s375 3064.5 444 607 s315 1444.5 444 667 s259 -175.5 444 488 s434 4657.5 574 548 s374 3037.5 574 608 s314 1417.5 574 668 s258 -202.5 574 489 s433 4630.5 444 549 s373 3010.5 444 609 s313 1390.5 444 669 s257 -229.5 444 490 s432 4603.5 574 550 s372 2983.5 574 610 s312 1363.5 574 670 s256 -256.5 574 491 s431 4576.5 444 551 s371 2956.5 444 611 s311 1336.5 444 671 s255 -283.5 444 492 s430 4549.5 574 552 s370 2929.5 574 612 s310 1309.5 574 672 s254 -310.5 574 493 s429 4522.5 444 553 s369 2902.5 444 613 s309 1282.5 444 673 s253 -337.5 444 494 s428 4495.5 574 554 s368 2875.5 574 614 s308 1255.5 574 674 s252 -364.5 574 495 s427 4468.5 444 555 s367 2848.5 444 615 s307 1228.5 444 675 s251 -391.5 444 496 s426 4441.5 574 556 s366 2821.5 574 616 s306 1201.5 574 676 s250 -418.5 574 497 s425 4414.5 444 557 s365 2794.5 444 617 s305 1174.5 444 677 s249 -445.5 444 498 s424 4387.5 574 558 s364 2767.5 574 618 s304 1147.5 574 678 s248 -472.5 574 499 s423 4360.5 444 559 s363 2740.5 444 619 s303 1120.5 444 679 s247 -499.5 444 500 s422 4333.5 574 560 s362 2713.5 574 620 s302 1093.5 574 680 s246 -526.5 574 501 s421 4306.5 444 561 s361 2686.5 444 621 s301 1066.5 444 681 s245 -553.5 444 502 s420 4279.5 574 562 s360 2659.5 574 622 s300 1039.5 574 682 s244 -580.5 574 503 s419 4252.5 444 563 s359 2632.5 444 623 s299 1012.5 444 683 s243 -607.5 444 504 s418 4225.5 574 564 s358 2605.5 574 624 s298 985.5 574 684 s242 -634.5 574 505 s417 4198.5 444 565 s357 2578.5 444 625 s297 958.5 444 685 s241 -661.5 444 506 s416 4171.5 574 566 s356 2551.5 574 626 s296 931.5 574 686 s240 -688.5 574 507 s415 4144.5 444 567 s355 2524.5 444 627 s295 904.5 444 687 s239 -715.5 444 508 s414 4117.5 574 568 s354 2497.5 574 628 s294 877.5 574 688 s238 -742.5 574 509 s413 4090.5 444 569 s353 2470.5 444 629 s293 850.5 444 689 s237 -769.5 444 510 s412 4063.5 574 570 s352 2443.5 574 630 s292 823.5 574 690 s236 -796.5 574 511 s411 4036.5 444 571 s351 2416.5 444 631 s291 796.5 444 691 s235 -823.5 444 512 s410 4009.5 574 572 s350 2389.5 574 632 s290 769.5 574 692 s234 -850.5 574 513 s409 3982.5 444 573 s349 2362.5 444 633 s289 742.5 444 693 s233 -877.5 444 514 s408 3955.5 574 574 s348 2335.5 574 634 s288 715.5 574 694 s232 -904.5 574 515 s407 3928.5 444 575 s347 2308.5 444 635 s287 688.5 444 695 s231 -931.5 444 516 s406 3901.5 574 576 s346 2281.5 574 636 s286 661.5 574 696 s230 -958.5 574 517 s405 3874.5 444 577 s345 2254.5 444 637 s285 634.5 444 697 s229 -985.5 444 518 s404 3847.5 574 578 s344 2227.5 574 638 s284 607.5 574 698 s228 -1012.5 574 519 s403 3820.5 444 579 s343 2200.5 444 639 s283 580.5 444 699 s227 -1039.5 444 520 s402 3793.5 574 580 s342 2173.5 574 640 s282 553.5 574 700 s226 -1066.5 574 521 s401 3766.5 444 581 s341 2146.5 444 641 s281 526.5 444 701 s225 -1093.5 444 522 s400 3739.5 574 582 s340 2119.5 574 642 s280 499.5 574 702 s224 -1120.5 574 523 s399 3712.5 444 583 s339 2092.5 444 643 s279 472.5 444 703 s223 -1147.5 444 524 s398 3685.5 574 584 s338 2065.5 574 644 s278 445.5 574 704 s222 -1174.5 574 525 s397 3658.5 444 585 s337 2038.5 444 645 s277 418.5 444 705 s221 -1201.5 444 526 s396 3631.5 574 586 s336 2011.5 574 646 s276 391.5 574 706 s220 -1228.5 574 527 s395 3604.5 444 587 s335 1984.5 444 647 s275 364.5 444 707 s219 -1255.5 444 528 s394 3577.5 574 588 s334 1957.5 574 648 s274 337.5 574 708 s218 -1282.5 574 529 s393 3550.5 444 589 s333 1930.5 444 649 s273 310.5 444 709 s217 -1309.5 444 530 s392 3523.5 574 590 s332 1903.5 574 650 s272 283.5 574 710 s216 -1336.5 574 531 s391 3496.5 444 591 s331 1876.5 444 651 s271 256.5 444 711 s215 -1363.5 444 532 s390 3469.5 574 592 s330 1849.5 574 652 s270 229.5 574 712 s214 -1390.5 574 533 s389 3442.5 444 593 s329 1822.5 444 653 s269 202.5 444 713 s213 -1417.5 444 534 s388 3415.5 574 594 s328 1795.5 574 654 s268 175.5 574 714 s212 -1444.5 574 535 s387 3388.5 444 595 s327 1768.5 444 655 s267 148.5 444 715 s211 -1471.5 444 536 s386 3361.5 574 596 s326 1741.5 574 656 s266 121.5 574 716 s210 -1498.5 574 537 s385 3334.5 444 597 s325 1714.5 444 657 s265 94.5 444 717 s209 -1525.5 444 538 s384 3307.5 574 598 s324 1687.5 574 658 s264 67.5 574 718 s208 -1552.5 574 539 s383 3280.5 444 599 s323 1660.5 444 659 nc 40.5 444 719 s207 -1579.5 444 540 s382 3253.5 574 600 s322 1633.5 574 660 nc 13.5 574 720 s206 -1606.5 574 data sheet s17594ej2v0ds 9 pd161608 table 2 ? 2. pad coordinate (4/5) pad no. name x y pad no. name x y pad no. name x y pad no. name x y 721 s205 -1633.5 444 781 s145 -3253.5 444 841 s85 -4873.5 444 901 s25 -6493.5 444 722 s204 -1660.5 574 782 s144 -3280.5 574 842 s84 -4900.5 574 902 s24 -6520.5 574 723 s203 -1687.5 444 783 s143 -3307.5 444 843 s83 -4927.5 444 903 s23 -6547.5 444 724 s202 -1714.5 574 784 s142 -3334.5 574 844 s82 -4954.5 574 904 s22 -6574.5 574 725 s201 -1741.5 444 785 s141 -3361.5 444 845 s81 -4981.5 444 905 s21 -6601.5 444 726 s200 -1768.5 574 786 s140 -3388.5 574 846 s80 -5008.5 574 906 s20 -6628.5 574 727 s199 -1795.5 444 787 s139 -3415.5 444 847 s79 -5035.5 444 907 s19 -6655.5 444 728 s198 -1822.5 574 788 s138 -3442.5 574 848 s78 -5062.5 574 908 s18 -6682.5 574 729 s197 -1849.5 444 789 s137 -3469.5 444 849 s77 -5089.5 444 909 s17 -6709.5 444 730 s196 -1876.5 574 790 s136 -3496.5 574 850 s76 -5116.5 574 910 s16 -6736.5 574 731 s195 -1903.5 444 791 s135 -3523.5 444 851 s75 -5143.5 444 911 s15 -6763.5 444 732 s194 -1930.5 574 792 s134 -3550.5 574 852 s74 -5170.5 574 912 s14 -6790.5 574 733 s193 -1957.5 444 793 s133 -3577.5 444 853 s73 -5197.5 444 913 s13 -6817.5 444 734 s192 -1984.5 574 794 s132 -3604.5 574 854 s72 -5224.5 574 914 s12 -6844.5 574 735 s191 -2011.5 444 795 s131 -3631.5 444 855 s71 -5251.5 444 915 s11 -6871.5 444 736 s190 -2038.5 574 796 s130 -3658.5 574 856 s70 -5278.5 574 916 s10 -6898.5 574 737 s189 -2065.5 444 797 s129 -3685.5 444 857 s69 -5305.5 444 917 s9 -6925.5 444 738 s188 -2092.5 574 798 s128 -3712.5 574 858 s68 -5332.5 574 918 s8 -6952.5 574 739 s187 -2119.5 444 799 s127 -3739.5 444 859 s67 -5359.5 444 919 s7 -6979.5 444 740 s186 -2146.5 574 800 s126 -3766.5 574 860 s66 -5386.5 574 920 s6 -7006.5 574 741 s185 -2173.5 444 801 s125 -3793.5 444 861 s65 -5413.5 444 921 s5 -7033.5 444 742 s184 -2200.5 574 802 s124 -3820.5 574 862 s64 -5440.5 574 922 s4 -7060.5 574 743 s183 -2227.5 444 803 s123 -3847.5 444 863 s63 -5467.5 444 923 s3 -7087.5 444 744 s182 -2254.5 574 804 s122 -3874.5 574 864 s62 -5494.5 574 924 s2 -7114.5 574 745 s181 -2281.5 444 805 s121 -3901.5 444 865 s61 -5521.5 444 925 s1 -7141.5 444 746 s180 -2308.5 574 806 s120 -3928.5 574 866 s60 -5548.5 574 926 s0 -7168.5 574 747 s179 -2335.5 444 807 s119 -3955.5 444 867 s59 -5575.5 444 927 nc -7195.5 444 748 s178 -2362.5 574 808 s118 -3982.5 574 868 s58 -5602.5 574 928 nc -7222.5 574 749 s177 -2389.5 444 809 s117 -4009.5 444 869 s57 -5629.5 444 929 g218 -7249.5 444 750 s176 -2416.5 574 810 s116 -4036.5 574 870 s56 -5656.5 574 930 g216 -7276.5 574 751 s175 -2443.5 444 811 s115 -4063.5 444 871 s55 -5683.5 444 931 g214 -7303.5 444 752 s174 -2470.5 574 812 s114 -4090.5 574 872 s54 -5710.5 574 932 g212 -7330.5 574 753 s173 -2497.5 444 813 s113 -4117.5 444 873 s53 -5737.5 444 933 g210 -7357.5 444 754 s172 -2524.5 574 814 s112 -4144.5 574 874 s52 -5764.5 574 934 g208 -7384.5 574 755 s171 -2551.5 444 815 s111 -4171.5 444 875 s51 -5791.5 444 935 g206 -7411.5 444 756 s170 -2578.5 574 816 s110 -4198.5 574 876 s50 -5818.5 574 936 g204 -7438.5 574 757 s169 -2605.5 444 817 s109 -4225.5 444 877 s49 -5845.5 444 937 g202 -7465.5 444 758 s168 -2632.5 574 818 s108 -4252.5 574 878 s48 -5872.5 574 938 g200 -7492.5 574 759 s167 -2659.5 444 819 s107 -4279.5 444 879 s47 -5899.5 444 939 g198 -7519.5 444 760 s166 -2686.5 574 820 s106 -4306.5 574 880 s46 -5926.5 574 940 g196 -7546.5 574 761 s165 -2713.5 444 821 s105 -4333.5 444 881 s45 -5953.5 444 941 g194 -7573.5 444 762 s164 -2740.5 574 822 s104 -4360.5 574 882 s44 -5980.5 574 942 g192 -7600.5 574 763 s163 -2767.5 444 823 s103 -4387.5 444 883 s43 -6007.5 444 943 g190 -7627.5 444 764 s162 -2794.5 574 824 s102 -4414.5 574 884 s42 -6034.5 574 944 g188 -7654.5 574 765 s161 -2821.5 444 825 s101 -4441.5 444 885 s41 -6061.5 444 945 g186 -7681.5 444 766 s160 -2848.5 574 826 s100 -4468.5 574 886 s40 -6088.5 574 946 g184 -7708.5 574 767 s159 -2875.5 444 827 s99 -4495.5 444 887 s39 -6115.5 444 947 g182 -7735.5 444 768 s158 -2902.5 574 828 s98 -4522.5 574 888 s38 -6142.5 574 948 g180 -7762.5 574 769 s157 -2929.5 444 829 s97 -4549.5 444 889 s37 -6169.5 444 949 g178 -7789.5 444 770 s156 -2956.5 574 830 s96 -4576.5 574 890 s36 -6196.5 574 950 g176 -7816.5 574 771 s155 -2983.5 444 831 s95 -4603.5 444 891 s35 -6223.5 444 951 g174 -7843.5 444 772 s154 -3010.5 574 832 s94 -4630.5 574 892 s34 -6250.5 574 952 g172 -7870.5 574 773 s153 -3037.5 444 833 s93 -4657.5 444 893 s33 -6277.5 444 953 g170 -7897.5 444 774 s152 -3064.5 574 834 s92 -4684.5 574 894 s32 -6304.5 574 954 g168 -7924.5 574 775 s151 -3091.5 444 835 s91 -4711.5 444 895 s31 -6331.5 444 955 g166 -7951.5 444 776 s150 -3118.5 574 836 s90 -4738.5 574 896 s30 -6358.5 574 956 g164 -7978.5 574 777 s149 -3145.5 444 837 s89 -4765.5 444 897 s29 -6385.5 444 957 g162 -8005.5 444 778 s148 -3172.5 574 838 s88 -4792.5 574 898 s28 -6412.5 574 958 g160 -8032.5 574 779 s147 -3199.5 444 839 s87 -4819.5 444 899 s27 -6439.5 444 959 g158 -8059.5 444 780 s146 -3226.5 574 840 s86 -4846.5 574 900 s26 -6466.5 574 960 g156 -8086.5 574 data sheet s17594ej2v0ds 10 pd161608 table 2 ? 2. pad coordinate (5/5) pad no. name x y pad no. name x y 961 g154 -8113.5 444 1021 g38 -9733.5 444 962 g152 -8140.5 574 1022 g36 -9760.5 574 963 g150 -8167.5 444 1023 g34 -9787.5 444 964 g148 -8194.5 574 1024 g32 -9814.5 574 965 g146 -8221.5 444 1025 g30 -9841.5 444 966 g144 -8248.5 574 1026 g28 -9868.5 574 967 g142 -8275.5 444 1027 g26 -9895.5 444 968 g140 -8302.5 574 1028 g24 -9922.5 574 969 g138 -8329.5 444 1029 g22 -9949.5 444 970 g136 -8356.5 574 1030 g20 -9976.5 574 971 g134 -8383.5 444 1031 g18 -10003.5 444 972 g132 -8410.5 574 1032 g16 -10030.5 574 973 g130 -8437.5 444 1033 g14 -10057.5 444 974 g128 -8464.5 574 1034 g12 -10084.5 574 975 g126 -8491.5 444 1035 g10 -10111.5 444 976 g124 -8518.5 574 1036 g8 -10138.5 574 977 g122 -8545.5 444 1037 g6 -10165.5 444 978 g120 -8572.5 574 1038 g4 -10192.5 574 979 g118 -8599.5 444 1039 g2 -10219.5 444 980 g116 -8626.5 574 1040 g0 -10246.5 574 981 g114 -8653.5 444 1041 gtestl -10273.5 444 982 g112 -8680.5 574 1042 nc -10326.5 574 983 g110 -8707.5 444 1043 nc -10379.5 444 984 g108 -8734.5 574 985 g106 -8761.5 444 986 nc -8788.5 574 987 nc -8815.5 444 988 g104 -8842.5 574 989 g102 -8869.5 444 990 g100 -8896.5 574 991 g98 -8923.5 444 992 g96 -8950.5 574 993 g94 -8977.5 444 994 g92 -9004.5 574 995 g90 -9031.5 444 996 g88 -9058.5 574 997 g86 -9085.5 444 998 g84 -9112.5 574 999 g82 -9139.5 444 1000 g80 -9166.5 574 1001 g78 -9193.5 444 1002 g76 -9220.5 574 1003 g74 -9247.5 444 1004 g72 -9274.5 574 1005 g70 -9301.5 444 1006 g68 -9328.5 574 1007 g66 -9355.5 444 1008 g64 -9382.5 574 1009 g62 -9409.5 444 1010 g60 -9436.5 574 1011 g58 -9463.5 444 1012 g56 -9490.5 574 1013 g54 -9517.5 444 1014 g52 -9544.5 574 1015 g50 -9571.5 444 1016 g48 -9598.5 574 1017 g46 -9625.5 444 1018 g44 -9652.5 574 1019 g42 -9679.5 444 1020 g40 -9706.5 574 data sheet s17594ej2v0ds 11 pd161608 table 2 ? 3. test pad coordinate (no bump) pad no. name x y 1 vss3 -236 -10370 2 vdc -211 -10260 3 vss -186 -10370 4 vdd -161 -10260 5 vcc2 -136 -10370 6 vcc1 -111 -10260 7 vdd1 -86 -10370 8 romrv -61 -10260 9 dotclk -36 -10370 10 vstby -11 -10260 11 resetb 14 -10370 12 csb 39 -10260 13 sck 64 -10370 14 sdi 89 -10260 15 sdo 114 -10370 16 atest3 139 -10260 17 spid 164 -10370 remark these pins belong to no bumps. therefore, ther e are not above mentioned pins inside block diagram. data sheet s17594ej2v0ds 12 pd161608 3. pin descriptions 3.1 power supply pins symbol pad no. i/o description v dd 57, 148 to 151 ? system power supply for internal logic. v ddio 153, 154, 170, 176, 182, 188, 207 ? voltage input pin for i/o logic. - connect to system v dd v ss 21, 48, 49, 113 to 120, 122 to 125, 127 to 130, 132 to 136, 167, 173, 179, 185, 191 ? system ground (0 v) vci 56, 138 to 147 ? step-up input voltage pin. - connect to voltage source between 2.5 to 3.3 v vcix2 83 to 89 output a power output pin for analog circuit that is generated from dc/dc converter circuit 1. connect a capacitor to this pin for stabilizati on. and vcix2 output voltage is limited to 5.5 v by internal limiter circuit. vci2 79 to 81 output a negative power output pin for analog circui t. connect a capacitor to this pin for stabilization. vci2 output voltage is ( ? vci). vlcd63 90 to 97 output a reference voltage level for gray-scale voltage generator. connect a capacitor to this pin for stabilization. vcom 3 to 5, 273 to 275 output output pin for tft-lcd common. vcomh 67 to 69, 99 to 101 output a regulator output for vcom output ?high? le vel. connect a capacitor to this pin for stabilization. vcoml 64 to 66, 76 to 78 output a regulator output for vcom output ?low? le vel. connect a capacitor to this pin for stabilization. exvr 109 input external reference of internal gamma resistor. - connect to v ss vcomr 110, 111 input this pin provides voltage reference for internal voltage regulator when register vdv [4:0] of 13.8 power supply control 4 (r0dh) set to ?01111?. - connect to an external voltage source for reference vgh 73 to 75 output a positive power output pin for gate driver. - connect a capacitor for stabilization vgl 70 to 72 output a negative power output pin for gate driver. - connect a capacitor for stabilization cxp, cxn 58 to 63 ? connect capacitor between cxp and cxn. cyp, cyn 50 to 55 ? connect capacitor between cyp and cyn. c1p, c1n 42 to 47 ? connect capacitor between c1p and c1n. c2p, c2n 34 to 39 ? connect capacitor between c2p and c2n. c3p, c3n 28 to 33 ? connect capacitor between c3p and c3n. data sheet s17594ej2v0ds 13 pd161608 3.2 interface pins (1/2) symbol pad no. i/o description rl 189, 190 input this pin?s setting is valid. source output direction is controlled as follows. - connect to v ddio : s0 s527 source driving mode. - connect to v ss : s527 s0 source driving mode. tb 186, 187 input input pin to select the gate driver scan direction. - connect to v ddio for gate scan from g0 to g219 - connect to v ss for gate scan from g219 to g0 bgr 183, 184 input input pin to select the color mapping. - connect to v ddio for blue-green-red mapping - connect to v ss for red-green-blue mapping rev 180, 181 input input pin to select the display reversion. - connect to v ddio for mapping data ?0? to maximum pixel voltage for normally white panel - connect to v ss for mapping data ?0? to minimum pixel voltage for normally black panel shut 192 to 194 input this pin?s setting is valid. power ci rcuit shut down is controlled as follows. high level: shut down (power off, standby sequence) low level: display on sequence (power circuit start operation sequentially) cm 262 to 264 input input pin to select 262 k-color or 8-color display mode. after entered 8-color display mode, only msb of the data red, green and blue will be considered. high level: 8-color display mode low level: 262 k-color display mode when set to 8-color mode, s0-s527 output vcix2 voltage and v ss levels for lcd driving. csb 161 to 163 input chip select input pin. high level: pd161608 is not selected and cannot be accessed. low level: pd161608 is selected and can be accessed. when not used this pin, leave it open. sck 159, 160 input serial clock input pin for a clo ck-synchronous serial interface. when not used this pin, leave it open. this pin is also pulled up inside ic. sdi 157, 158 input serial data input pin for a clock-synchronous seri al interface. the input data is latched by the rising edge of sck signal. when not used this pin, leave it open. this pin is also pulled up inside ic. sdo 155, 156 output serial data output pin for a clock-synchronous se rial interface. the data is output at the falling edge of sck signal. when not used this pin, leave it open. spid 171, 172 input id selection pin for the spi serial interface. when sending serial data, the ?id? bit must much with the logic stage of this pin. high level: id = 1 low level: id = 0 dotclk 195 to 197 input dot clock signal for rgb interface. a non-stop external clock must be provided to that pin even at front or back porch non-display period. display data are fetched at rising edge of dotclk enable 204 to 206 input data enabling signal for using rgb interface. high level: valid (possible to access), it qualifies the valid are of display data input. low level: invalid (not possible to access) cad 177, 178 input although it is intact, since potential fi xation is required, give as low fixation. tmb 126 input gamma initial value setting pin. high level: mode 1 low level: mode2 this pin is pulled up internally ic. so if this pin leave open, mode1 is selected. data sheet s17594ej2v0ds 14 pd161608 (2/2) symbol pad no. i/o description rr [5:0], gg [5:0], bb [5:0] 208 to 225, 226 to 243, 244 to 261 input graphic data input pins: - rr [5:0] : red data - 6-bit - gg [5:0] : green data - 6-bit - bb [5:0] : blue data - 6-bit hsync 198 to 206 input horizontal synchr onous signal. active level is low. vsync 201 to 203 input vertical synchronous signal. active level is low. resetb 164 to 166 input reset input pin. initializes the ic when low. 3.3 display pins symbol pad no. i/o description s0 to s527 395 to 658, 663 to 926 output source driver output pins s0, s3, s6, ... s (3n ? 2): red display (r) (bgr = low) s1, s4, s7, ... s (3n ? 1): green display (g) (bgr = low) s2, s5, s8, ... s (3n) : blue display (b) (bgr = low) g0 to g219 929 to 985, 988 to 1040 output gate driver output pins. these pins output vgh, vgl level. 3.4 internal power regula tor pins for logic circuit symbol pad no. i/o description regvdd 174, 175 input internal power regulator control input pin. when regvdd is fixed to l level, the internal regulated power (rvdd) is used as internal logic supply voltage. be sure to set v ddio to v dd . when regvdd is fixed to h level, the external logic power (v dd ) is used as internal logic supply voltage. be sure to set v ddio v dd . rvdd 103 to 108 output internal power regulated-v ddio output. when regvdd is h level, rvdd is connected to v dd pin. and connect with 1.0 f capacitor between v ss . when regvdd is l level, rvdd is outputted regulator voltage. and connect with 1.0 f capacitor between v ss . 3.5 control pins symbol pad no. i/o description testa 98 output use as eeprom read voltage output. connect to stabilizer capacitor. testb 41 output this pin is auxiliary output of vcix 2. connect to stabilizer capacitor as necessary. testc 40 ? unused. leave this pin open. cdum0 8 to 10 input this pin is us ed for test. leave this pin open. cdum1 11 to 13 input this pin is us ed for test. leave this pin open. testin1 to testin5 168, 169, 265 to 267 input these pins are used for test. normally, leave it open. testout 268 to 270 output these pins are used for test. normally, leave it open. gtestr 392 output gate driver test output pin. leave this pin open. gtestl 1041 output gate driver test output pin. leave this pin open. data sheet s17594ej2v0ds 15 pd161608 4. functional description 4.1 external interface (rgb interface) the pd161608 supports rgb interface as an external interface for motion picture display. rgb display data of one line (s0 to s527) are latched to the data latch register through parallel data bus (pd) in orderly. if one line data is latched, data latch register data is transferred to the source driver amp and then the display is outputted . the display data (pd17-pd0) are written according to the c ontrol of the data enable signal (enable) in synchronization with the vsync, hsync, and dotclk signals. this performs flicker-free upd ating of the screen. refer to 6. external display interface . 4.2 system interface the pd161608 builds in a serial peripheral interface port (spi). this system interface transfers the data to the internal control register for power control, display control, gamma adjustment. table 4 ? 1. register selection (serial peripheral interface) r/w bit rs bit operations 0 0 writes indexes into ir 0 1 writes instruction into control registers 1 0 status read 1 1 instruction data read 4.3 gray-scale voltage generator the gray-scale voltage generator generates lcd driver volt ages which correspond to the gray-scale levels as specified in the gray-scale -adjusting resistor. 262,144 possible colors can be displayed at the same time . for details, refer to 16. gamma adjustment register . 4.4 display timing control the display timing generator generates the interface signals such source output, common output and gate driver from rgb interface signal input. 4.5 built-in power supply circuit the built-in power supply circuit generates (powers of ) vcix2, vlcd63, vgh, vgl and vcom voltages that are corresponded to display the tft-lcd panel. 4.6 lcd display circuit the lcd display circuit consists of 528 source drivers (s0 to s527). display pattern data are latched when 528-bit data have arriv ed. the latched data then enable the source drivers to generate drive waveform outputs. the rl pin can change t he shift direction of 528-bit data by selecting an appropriate direction for the device -mounted configuration. data sheet s17594ej2v0ds 16 pd161608 5. power supply circuit figure 5 ? 1 shows a configuration of the vo ltage generation circuit for the pd161608. the dc/dc converter circuits consist of dc/dc converter circuits 1, 2 and 3. dc/dc conv erter circuit 1 doubles the voltage supplied to vci, and that voltage is doubled or tripled in dc/dc converter circuit 2. and dc/dc converter circuit 3 flips the vci level and generates the vci2 level. these dc/dc converter circui ts generate power supplies vcix2, vgh, vgl. figure 5 ? 1. configuration of the internal power supply circuit 1st booster 2nd and 3rd booster vlcd63 regulator band gap reference 2.0 v vrh [3:0] vdv [4:0] bt [2:0] vcm [5:0] comh vcom adjustment l/s v dd vci2 gray-scale amplifier vci2 to source driver to gate driver (top) to gate driver (bottom) vgh vgl vcomr vcoml vcoml vcom vlcd63 vcix2 shottky diode shottky diode shottky diode vci 0.1 f 6.3 v 1 f 6.3 v 1 f 6.3 v 1 f 6.3 v 1 f 6.3 v 1 f 16 v 1 f 6.3 v 1 f 16 v 1 f 16 v 1 f 6.3 v 1 f 6.3 v 1 f 6.3 v 1 f 16 v 0.1 f 6.3 v 0.1 f 6.3 v 0.1 f 16 v 0.1 f 16 v cxp cxn cyp cyn c1p c1n c2p c2n c3p c3n t/c power shift regulator v ddio v dd rvdd regvdd to internal logic low active vcomh vcomh testb testa eeprom vci regulator coml regulator read voltage regulator data sheet s17594ej2v0ds 17 pd161608 5.1 pattern diagrams for voltage setting the following figure shows a pattern diagram of the voltage setting and an example of waveforms. figure 5 ? 2. pattern diagram vgh bt [2:0] (r03h) bt [2:0] (r03h) vci reference (2.0 v) vcix2 (vci) x ( ? 1) vlcd63 vci x 2 (vci 2.75 v), 5.5 v (vci > 2.75 v) vci2 v ss vgl vcomh vrh [3:0] r0dh vcm [5:0] r1eh vdv [4:0] r0eh vcoml caution adjust the conditions of vcix2-vvld63 > 0.5 v and vcoml-vci2 > 0.5 v with loads because they differ depending on the display load to be driven. v com vgh vlcd63 vcomh vcoml vgl sn (source driver output) gn data sheet s17594ej2v0ds 18 pd161608 5.2 recommendation wiring resistance value to each pin the wiring resistance value to recommend is shown below. si nce wiring resistance influences the current capability of a power supply, it asks for panel design so that it may become below recommendation value. pin name wiring resistance value ( ) v ss < 10 v dd < 20 v ddio < 20 vci < 10 testa < 30 testb < 30 rvdd < 10 vlcd63 < 10 vcix2 < 10 vgh < 30 vgl < 10 vci2 < 10 vcomh < 10 vcoml < 10 vcom < 10 cxp < 10 cxn < 10 cyp < 10 cyn < 10 c1p < 10 c1n < 10 c2p < 30 c2n < 30 c3p < 30 c3n < 30 data sheet s17594ej2v0ds 19 pd161608 5.3 recommendation capacitance value to each pin the recommendation value of a capacitor is shown below. please determine a capacity value, after a module fully evaluates. pin name capacitance ( f) v dd 0.1 to 1 v ddio 0.1 to 1 vci 0.1 to 1 testa 1 to 2.2 testb 1 to 2.2 rvdd 1 to 4.7 vlcd63 1 to 4.7 vcix2 1 to 4.7 vgh 0.47 to 1 vgl 0.47 to 1 vci2 1 to 4.7 vcomh 1 to 4.7 vcoml 1 to 4.7 cxp cxn 0.1 to 2.2 cyp cyn 0.1 to 2.2 c1p c1n 0.1 to 2.2 c2p c2n 0.1 to 1 c3p c3n 0.1 to 1 5.4 recommendation of a schottky diode it recommends inserting a schottky diod e between vci-vcix2, vci-vgh, and vgl-v ss . please fully evaluate by the module. recommendation specification forward voltage (v f ): 0.6 v at i f = 200 ma reverse current (i r ): 1 a at v r = 10 v dc reverse voltage (v r ): more than 20 v data sheet s17594ej2v0ds 20 pd161608 6. external display interface 6.1 rgb interface the following interfaces are available as external display interface. figure 6 ? 1. interface signal mapping from graphic controller lcdc pd161608 resetb csb sck sdi vsync hsync enable dotclk pd [17:0] 18 cm shut tb rl 6.2 18-bit rgb interface display operation is synchronized with vsync, hsync, and dotclk signals. data for display is transferred via 18-bit rgb data bus (pd17-pd0). figure 6 ? 2. rgb data arrange in the 18-bit rgb interface mode r5 input 1-pixel rgb arrange g5 b5 b4 b3 b2 b1 b0 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0 pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 11 pd 10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 remark 262,144-color display is possible using the 18-bit rgb interface. data sheet s17594ej2v0ds 21 pd161608 figure 6 ? 3. 18-bit rgb interface timing dotclk rgb 1a rgb 2a rgb 3a rgb 4a rgb 174a rgb 175a rgb 176a rgb 1b rgb 2b rgb 3b pd [17:0] hsync n line valid data transfer area enable 176* dotclk (18-bits bus i/f) n + 1 line h blank area data sheet s17594ej2v0ds 22 pd161608 7. system interface 7.1 serial data transfer it indicates serial data transfer as follows. (1) the pd161608 initiates serial data transfer by transferring t he start byte at the falling edge of csb input. it ends serial data transfer at the rising edge of csb input. (2) the pd161608 is selected when the 6-bit chip address in t he start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the pd161608. the pd161608, when selected, receives the subsequent data string. (3) the id pin can determine the least sign ificant bit of the identific ation code. the five upper bits must be 01110. two different chip addresses must be assigned to a single pd161608 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be wr itten to the index register or status can be read, and when rs = 1, an instruction can be issued. read or write is selected according to the eighth bit of the start byte (r/w bit). the dat a is read when the r/w bit is 0, and is written when the r/w bit is 1. (4) after reading the start byte, the pd161608 reads or writes the subseque nt data byte-by-byte. the data is transferred with the msb first. all pd161608 instructions are 16 bits. two by tes are read with the msb first, and then the instructions are internally executed. after the start byte has been read, the first byte is transmitted internally as the upper eight bits of the instruction and the second byte is transm itted internally as the lower ei ght bits of the instruction. table 7 ? 1. start byte format transfer bit s 1 2 3 4 5 6 7 8 device id code start byte format transfer start 0 1 1 1 0 id rs r/w caution id pin selects id bit. table 7 ? 2. rs and r/w bit function r/w bit rs bit operations 0 0 writes indexes into ir 0 1 writes instruction into control registers 1 0 status read 1 1 instruction data read figure 7 ? 1. instruction of serial data transfer ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 d15 input instruction 1st transfer (upper) 2nd transfer (lower) d14 d13 d12 d11 d10 d9 d8 instruction code d7 d6 d5 d4 d3 d2 d1 d0 data sheet s17594ej2v0ds 23 pd161608 7.2 procedure for transfer on clock synchronized serial bus interface figure 7 ? 2. timing basic data transfer through clock-synchronized serial bus interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 rs r/w id db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 111 0 hi-z device id start byte index register setting instruction data read instruction transfer start transfer end csb (input) (input) (input) (output) sck sdi sdo 0 figure 7 ? 3. timing of consecutive data-transfer th rough clock-synchronized serial bus interface 1234567 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 csb start end instruction execution time start byte instruction 1: upper instruction 2: lower (input) (input) (input) sck sdi caution the first byte after the start byte is always the upper eight bits. data sheet s17594ej2v0ds 24 pd161608 8. timing specification the pd161608 executes power up/down by internal sequential timing. following table shows ac timing characteristics and figure 8 ? 1 shows horizontal/vertical pixel clock timing (262 k-full screen timing ) . 8.1 ac timing requirements 260 k-color mode and common characteristics symbol min. typ. max. unit vertical frequency (refresh) f v 57.2 60.1 63.1 hz horizontal frequency (line) f h 12.8 13.5 14.1 khz dotclk frequency f dotclk 2.51 2.64 2.77 mhz dotclk clock period t dotclk 398 379 361 ns horizontal back porch t hbp 10 t dotclk horizontal front porch t hfp 10 t dotclk horizontal blanking period t hbp + t hfp 20 t dotclk horizontal display area h disp 176 t dotclk horizontal cycle hcycle 196 t dotclk vsync back porch t vbp 3 line vsync front porch t vfp 1 line vertical blanking period t vbp + t vfp 4 line vertical display area v disp 220 line vertical cycle vcycle 224 line 8-color mode specified characteristics symbol min. typ. max. unit vertical frequency (refresh) f v f v8 ? 5% f v8 f v8 +5% hz horizontal frequency (line) f h f h8 ? 5% f h8 f h8 +5% khz dotclk frequency f dotclk f dotclk8 ? 5% f dotclk8 f dotclk8 +5% mhz dotclk clock period t dotclk t dotclk8 ? 5% t dotclk8 t dotclk8 +5% ns vertical partial back porch v pbp 0 219 line vertical active area v pdsp 1 220 line remark f v8 : 30.1 to 60.1hz, f h8 : 6.73 to 13.5 khz, f dotclk8 : 1.32 to 2.64 mhz, t dotclk8 : 758 to 379 ns rgb common timing characteristics symbol min. typ. max. unit dotclk frequency f dotclk 2.51 2.64 2.77 mhz dotclk period t dotclk 398 379 361 ns vertical sync setup time t vsys 30 ns vertical sync hold time t vsyh 30 ns horizontal sync setup time t hsys 30 ns horizontal sync hold time t hsyh 30 ns phase difference of sync signal falling edge t hv 0 176 t dotclk dotclk low period t ckl 150 ns dotclk high period t ckh 150 ns data setup time t ds 40 ns data hold time t dh 40 ns data sheet s17594ej2v0ds 25 pd161608 figure 8 ? 1. 262 k-full screen timing hbp = 10 vbp = 3 dotclk horizontal timing vertical timing pixel clock timing dotclk enable enable hsync hsync hsync vsync vsync t vsys t dotclk t hsys t hv t ds t dh t ckl t ckh t hsyh t vsyh data dummy dummy d0, d1 d174, d175 data data hcycle = 196 vcycle = 224 line hfp = 10 vfp = 1 line 219 hdisp = 176 vdisp = 220 line data sheet s17594ej2v0ds 26 pd161608 figure 8 ? 2. 8-color mode timing vsync 8-color mode vertical timing mode conversion timing vbp = 3 vpbp vpdsp line 219 line 0 vfp = 1 vcycle = 224 line vdisp = 220 line vsync color mode hsync cm 262 k-color mode 8-color mode 262 k-color mode enable data sheet s17594ej2v0ds 27 pd161608 9. power up sequence the pd161608 operates power up and display on by v dd , shut, dotclk, hsync, and vsync as shown as following figure. figure 9 ? 1. power up sequence timing 123456789101112 disp off disp on vci shut dotclk hsync vsync display high voltage disp v dd v ddio t dd-ci t rs-shut t clk-shut t shut-lcd t shut-on t p-shut /res table 9 ? 1. power up ac characteristics characteristics symbol min. typ. max. unit vdd/vci on to falling edge of shut t p-shut 1 ms /res to falling edge of shut t rs-shut 10 s dotclk input to falling edge of shut t clk-shut 1 clk falling edge of shut to lcd power on t shut-lcd 128 ms 166 ms falling edge of shut to display start 1h = 196 dotclk, 1frame = 224h, dotclk = 2.64 mhz t shut-on 10 frame remark t dd-ci can be 0 s, > 0 s, therefore, v dd , v ddio and vci power up sequence should not have any impact on the driver/display functionalities/performance. data sheet s17594ej2v0ds 28 pd161608 10. recovery sequence when a power supply turns off momentarily the pd161608 operates power up and display on by v dd , shut, dotclk, hsync, and vsync as shown as following figure when a power supply turns off momentarily. vci shut dotclk hsync 1 2 3 4 5 6 7 8 9 10 11 12 vsync disp disp off disp on t sd-lcd t sd-on voltage display high v dd v ddio /res data sheet s17594ej2v0ds 29 pd161608 11. power down sequence the pd161608 operates power off and display off by v dd, shut, dotclk, hsync, and sync as shown as following figure. figure 11 ? 1. power down sequence timing 1 vci shut dotclk hsync vsync power on power off display off normal display white data display white data out (min. pixel voltage) normal display normal drive scanning 1-frame display high voltage disp sn vcom gn v ss v ss v ss v dd v ddio 2 t ci-dd t off-vdd t shut-off vci 3 table 11 ? 1. power down ac characteristics characteristics symbol min. typ. max. unit 50 ms rising edge of shut to display off, 1h = 196 dotclk, 1frame = 224h, dotclk = 2.64 mhz t shut-off 3 frame input-signal-off to v dd /vci off t off-vdd 1 s remark t ci-dd can be 0 s, > 0 s, therefore, v dd , v ddio and vci power down sequence should not have any impact on the driver/display functionalities/performance. data sheet s17594ej2v0ds 30 pd161608 12. instructions 12.1 outline the operation of the pd161608 is determined by signals sent through seri al peripheral interface (spi). these signals, which include the register selection signal (rs), the read/writ e signal (r/w), and the internal 16-bit data bus signals (ib15 to ib0), make up the pd161608 instructions. there are five categories of instructions that: (1) specify the index (2) read the status (3) control the display (4) control power management (5) set gray-scale level for the in ternal gray-scale palette table data sheet s17594ej2v0ds 31 pd161608 12.2 instruction table u pp e r code lower code register no. register name ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 - index * * * * * * * * * id6 id5 id4 id3 id2 id1 id0 - status read l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 01h driver output control 0 0 rev 0 bgr sm tb rl mux7mux6mux5mux4mux3mux2mux1mux0 02h lcd driving waveform control 000000b/ceor0nw6nw5nw4nw3nw2nw1nw0 03h power supply cotrol 1 dct3 dct2 dct1 dct0 bt2 bt1 bt0 0 dc3 dc2 dc1 dc0 a p2 a p1 a p0 0 04h setting disabled 05h setting disabled 06h setting disabled 07h setting disabled 08h setting disabled 09h setting disabled 0ah setting disabled 0bh frame cycle control no1 no0 sdt1 sdt0 eq1 eq0 pt1 pt0 0 0 0 0 0 0 0 0 0ch setting disabled 0000000000000100 0dh power supply control 3 0000000000notp1dumm y 1 vrh3 vrh2 vrh1 vrh0 0eh power supply control 4 notp2 dumm y 2 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 0 0 0 0 0 0fh gate scan start position 0 0 0 0 0 0 0 0 scn7 scn6 scn5 scn4 scn3 scn2 scn1 scn0 10h setting disabled 11h setting disabled 12h setting disabled 13h setting disabled 14h setting disabled 15h setting disabled 16h horizontal porch 1 0 1 0 1 1 1 1 0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 17h vertical porch 0 0 0 0 0 0 0 0 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 18h setting disabled 19h setting disabled 1ah setting disabled 1bh setting disabled 1ch setting disabled 1dh setting disabled 1eh power supply control 5 00000000notp3dumm y 3vcm5vcm4vcm3vcm2vcm1vcm0 1fh setting disabled 20h setting disabled 21h setting disabled 22h setting disabled 23h setting disabled 24h setting disabled 25h setting disabled 26h setting disabled 27h setting disabled 28h software reset 29h setting disabled 2ah setting disabled 2bh setting disabled 2ch setting disabled 2dh setting disabled 2eh setting disabled 2fh setting disabled 30h gamma control (1) 000notp4dumm y 4 pkp12 ( 0 ) pkp11 ( 0 ) pkp10 ( 0 ) 00000pkp02 ( 1 ) pkp01 ( 0 ) pkp00 ( 0 ) 31h gamma control (2) 0 0 0 0 0 pkp32 ( 0 ) pkp31 ( 0 ) pkp30 ( 0 ) 00000pkp22 ( 0 ) pkp21 ( 0 ) pkp20 ( 0 ) 32h gamma control (3) 0 0 0 0 0 pkp52 ( 0 ) pkp51 ( 0 ) pkp50 ( 1 ) 00000pkp42 ( 0 ) pkp41 ( 0 ) pkp40 ( 1 ) 33h gamma control (4) 00000prp12 ( 0 ) prp11 ( 1 ) prp10 ( 0 ) 00000prp02 ( 0 ) prp01 ( 1 ) prp00 ( 0 ) 34h gamma control (5) 00000pkn12 ( 1 ) pkn11 ( 1 ) pkn10 ( 0 ) 00000pkn02 ( 1 ) pkn01 ( 1 ) pkn00 ( 0 ) 35h gamma control (6) 00000pkn32 ( 1 ) pkn31 ( 1 ) pkn30 ( 1 ) 00000pkn22 ( 1 ) pkn21 ( 1 ) pkn20 ( 1 ) 36h gamma control (7) 00000pkn52 ( 0 ) pkn51 ( 1 ) pkn50 ( 1 ) 00000pkn42 ( 1 ) pkn41 ( 1 ) pkn40 ( 1 ) 37h gamma control (8) 00000prn12 ( 0 ) prn11 ( 1 ) prn10 ( 0 ) 00000prn02 ( 0 ) prn01 ( 1 ) prn00 ( 0 ) 38h setting disabled 39h setting disabled 3ah gamma control (9) 000vrp14 ( 1 ) vrp13 ( 1 ) vrp12 ( 1 ) vrp11 ( 1 ) vrp10 ( 1 ) 0000vrp03 ( 0 ) vrp02 ( 0 ) vrp01 ( 0 ) vrp00 ( 0 ) 3bh gamma control (10) 000vrn14 ( 1 ) vrn13 ( 1 ) vrn12 ( 1 ) vrn11 ( 1 ) vrn10 ( 1 ) 0000vrn03 ( 0 ) vrn02 ( 0 ) vrn01 ( 0 ) vrn00 ( 0 ) 3ch setting disabled 3dh setting disabled 3eh setting disabled 3fh setting disabled 52h power supply control 6 dcsel vghon vcix2on vci2on vglon vl63on vcomon dcon 0 0 1 1 1 1 0 0 54h vgh off setting 000000000000000vghoff 60h eeprom mode setting 0000000000000ep _ read ep _ write ep _ pwr 61h eeprom operation control 0000000000000ie2opc2ie2opc1ie2opc0 70h power supply control 3 parit y 00dumm y 5dumm y 1 vrh3 vrh2 vrh1 vrh0 71h power supply control 4 parit y dumm y 6dumm y 2 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 72h power supply control 5 parit y dumm y 7dumm y 3vcm5vcm4vcm3vcm2vcm1vcm0 73h gamma control 1 parit y dumm y 8dumm y 4 pkp12 pkp11 pkp10 pkp02 pkp01 pkp00 74h gamma control 2 parit y 0 pkp32 pkp31 pkp30 0 pkp22 pkp21 pkp20 75h gamma control 3 parit y 0 pkp52 pkp51 pkp50 0 pkp42 pkp41 pkp40 76h gamma control 4 parit y 0 prp12 prp11 prp10 0 prp02 prp01 prp00 77h gamma control 5 parit y 0 pkn12 pkn11 pkn10 0 pkn02 pkn01 pkn00 78h gamma control 6 parit y 0 pkn32 pkn31 pkn30 0 pkn22 pkn21 pkn20 79h gamma control 7 parit y 0 pkn52 pkn51 pkn50 0 pkn42 pkn41 pkn40 7ah gamma control 8 parit y 0 prn12 prn11 prn10 0 prn02 prn01 prn00 7bh gamma control 9 parit y vrp12 vrp11 vrp10 0 vrp03 vrp02 vrp01 vrp00 7ch gamma control 10 parit y vrn12 vrn11 vrn10 0 vrn03 vrn02 vrn01 vrn00 7dh gamma control 9,10 parit y 0 0 vrn14 vrn13 0 0 vrp14 vrp13 software reset there are no actual registers. when these registers are read, value is '0'. remark *: don?t care data sheet s17594ej2v0ds 32 pd161608 13. instruction descriptions ensure that you are aware of the assignm ents of instruction bits (ib15-ib0) for each interface that ar e illustrated below. 13.1 index register (ir) the index instruction specifies the contro l register indexes (r00h to r7dh). it sets the register number in the range of 0000000 to 1111111 in binary form. however, do not access to index register and instruction bi t that is not allocated in index register. w r/w rs 0 * ib15 ib14 ib13 id6 id5 id4 id3 id2 id1 id0 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 ******** remark * : don?t care 13.2 status read (sr) the status read instruction r eads the internal status of the pd161608. l7-l0 : indicate the driving raster-ro w position where the liquid crys tal display is being driven. r r/w rs 0 l7 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 13.3 driver output control (r01h) w r/w rs 1 0 0 rev 0 bgr sm tb rl mux7 ib15 ib14 ib13 mux6 mux5 mux4 mux3 mux2 mux1 mux0 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 rev : displays all character and graphics display sections with re versal when rev = ?1?. since the gray-scale level can be reversed, display of the same data is enabled on normally white and normally black panels. source output level is indicated below. rev rgb data source output level vcom = h vcom = l 1 00000h : 3ffffh v63 : v0 v0 : v63 0 00000h : 3ffffh v0 : v63 v63 : v0 sm : change the division of gate driver. sm = 0: odd/even division (interlace mode) is selected. sm = 1: upper/lower division is selected. select the di vision mode according to the mounting method (por = 0) data sheet s17594ej2v0ds 33 pd161608 tb : selects the output shift dire ction of the gate driver. tb = 0: g219 shifts to g0. tb = 1: g0 shifts to g219. rl : selects the output shift direct ion of the source driver. rl = 0: start point: s527, end point s0 rl = 1: start point: s0, end point s527 caution about tb, rl rev, and bgr function, it is initialized by the level of a hardware pin when hardware reset and software reset is performed. by changing the level of the hardware pin, an internal state is also changeable. after sending the data of r01h by software, the data sent by software becomes valid. in this case, a setup of a hardware pin becomes invalid until it performs hardware reset. in addition, when tb, rl, rev, and bgr pin are changed, the timing which becomes 2 kinds valid inside ic is as follows. (1) about rl and tb function, these setup becom es valid inside ic in the top of a frame. (2) about rev and bgr function, these setup becomes valid inside ic immediately. data sheet s17594ej2v0ds 34 pd161608 bgr : selects the data sheet s17594ej2v0ds 35 pd161608 13.4 lcd driving waveform control (r02h) w r/w rs 1 0 0 0 b/c eor ib15 ib14 ib13 nw6 nw5 nw4 nw3 nw2 nw1 nw0 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 000 0 b/c : when b/c = 0, it performs scanniing in every frame for lcd drive. when b/c = 1, n-raster-row inversion waveform is generated and alternates in each raster-row specified by bits eor and nw6-nw0 in the lcd-driving-waveform control register. for details, refer to 20. n-raster-row reserved ac drive (default: b/c = 1). eor : when the n-raster-row inversion waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eor fo r alternating drive. eor is used wh en combining the set values of the number of the lcd drive raster-row an d the n raster-row does not alternate the lcd. for details, refer to 20. n- raster-row reserved ac drive (default: eor = 1). nw6-nw0 : specify the number of raster-rows n t hat will alternate at the n-raster-row inversion waveform setting (b/c = 1). nw6-nw0 alternate for every set value + 1 raster-row, and the first to the 128th raster-rows can be selected (default: nw6-nw0 = 0) data sheet s17594ej2v0ds 36 pd161608 13.5 power supply control 1 (r03h) w r/w rs 1 dct3 bt2 0 dc3 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 dct2 dct1 dct0 bt1 bt0 dc2 dc1 dc0 ap2 ap1 ap0 0 dct3-dct0: set the step-up cycle of the step-up circuit for 8-color mode (cm = v ddio ). when the cycle is accelerated, the driving ability of the step-up circ uit increases, but its current consumpt ion increases as well. adjust the cycle taking into account the display quality and power consumption. dct3 dct2 dct1 dct0 step-up cycle 0 0 0 0 f line x 14 0 0 0 1 f line x 11 0 0 1 0 f line x 9 0 0 1 1 f line x 7 0 1 0 0 f line x 6 0 1 0 1 f line x 5 0 1 1 0 f line x 4 0 1 1 1 f line x 3 1 0 0 0 f line x 2 1 0 0 1 f line x 1 1 0 1 0 f osc /24 1 0 1 1 f osc /40 1 1 0 0 f osc /48 1 1 0 1 f osc /56 1 1 1 0 f osc /64 1 1 1 1 f osc /80 remark f line: horizontal frequency (f h typ. 13.5 khz) f osc : dotclk frequency (f dotclk typ. 2.64 mhz) caution when dctn setting is changed to f line x n (dct3-dct0 = 0000 to 1001), the change of the setting is updated following 2 cases. 1. power up sequence using shut pin 2. from the head of the frame immediately after changing the level of cm pin data sheet s17594ej2v0ds 37 pd161608 bt2-bt0: the output factor of step-up is switc hed. adjust scale factor of the dc/dc converter circuit by the voltage used. bt2 bt1 bt0 vcix2 vgh output vgl output 0 0 0 2 x vci 6 x vci ? 5 x vci 0 0 1 2 x vci 6 x vci ? 4 x vci 0 1 0 2 x vci 6 x vci ? 3 x vci 0 1 1 2 x vci 5 x vci ? 5 x vci 1 0 0 2 x vci 5 x vci ? 4 x vci 1 0 1 2 x vci 5 x vci ? 3 x vci 1 1 0 2 x vci 4 x vci ? 4 x vci 1 1 1 2 x vci 4 x vci ? 3 x vci remark when set to 8-color mode (cm = ?h?), vgl output voltage is fixed to ? ? 3 x vci?. dc3-dc0: set the step-up cycle of the step-up circuit for 262 k-color mode (cm = v ss ). when the cycle is accelerated, the driving ability of the step-up circ uit increases, but its current consumpt ion increases as well. adjust the cycle taking into account the display quality and power consumption. dc3 dc2 dc1 dc0 step-up cycle 0 0 0 0 f line x 14 0 0 0 1 f line x 11 0 0 1 0 f line x 9 0 0 1 1 f line x 7 0 1 0 0 f line x 6 0 1 0 1 f line x 5 0 1 1 0 f line x 4 0 1 1 1 f line x 3 1 0 0 0 f line x 2 1 0 0 1 f line x 1 1 0 1 0 f osc /24 1 0 1 1 f osc /40 1 1 0 0 f osc /48 1 1 0 1 f osc /56 1 1 1 0 f osc /64 1 1 1 1 f osc /80 remark f line: horizontal frequency (f h typ. 13.5 khz) f osc : dotclk frequency (f dotclk typ. 2.64 mhz) caution when dcn setting is changed to f line x n (dc3-dc0 = 0000 to 1001), the change of the setting is updated following 2 cases. 1. power up sequence using shut pin 2. from the head of the frame immediately after changing the level of cm pin data sheet s17594ej2v0ds 38 pd161608 ap2-ap0: adjust the amount of current from t he stable-current source in the inte rnal operational amplifier circuit. when the amount of current becomes la rge, the driving ability of the oper ational-amplifier circuits increase. adjust the current taking into account the power consumpti on. during times when there is no display, such as when the system is in a sleep mode. ap2 ap1 ap0 amount of current in operational amplifier 0 0 0 smallest 0 0 1 small 0 1 0 medium small 0 1 1 medium 1 0 0 large small 1 0 1 large medium 1 1 0 large 1 1 1 largest data sheet s17594ej2v0ds 39 pd161608 13.6 frame cycle control (r0bh) w r/w rs 1 no1 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 00000000 no0 eq1 pt1 pt0 eq0 sdt1 sdt0 no1, no0 : set the gate non-overlap period. no1 no0 gate non-overlap period 0 0 0 clock cycle 0 1 4 clock cycle 1 0 6 clock cycle 1 1 8 clock cycle remark clock cycle: dotclk cycle sdt1, sdt0 : specify the timing on which a source signal is output after falling edge of a gate signal. sdt1 sdt0 delay amount of the source output 0 0 4 clock cycle 0 1 4 clock cycle 1 0 4 clock cycle 1 1 4 clock cycle remark clock cycle: dotclk cycle eq1, eq0 : equalized period is added as specified by bits of eq 1-eq0. the equalization signa l is output for scan line. eq1 eq0 equalizing period 0 0 not equalized 0 1 18 clock cycle 1 0 26 clock cycle 1 1 a:b ratio = 1:7 note remark clock cycle: dotclk cycle note in power up sequence, only when being setup before starting shut pin, the setup of this command is valid. pt1, pt0 : set the division ratio of clocks for internal operation. internal operations are driven by clocks which frequency are divided according to the pt1, pt0 setting. pt1 pt0 internal operation clock frequency 0 0 f osc /1 0 1 reserved 1 0 reserved 1 1 reserved remark f osc = dotclk frequency data sheet s17594ej2v0ds 40 pd161608 sdt [1:0] hi-z no [1:0] eq [1:0] vcom 1h period 1h period equalizing period non overlap time source output delay time ab (veq) note gn gn + 1 sn note the signal in parenthesis are shown internal signal. data sheet s17594ej2v0ds 41 pd161608 13.7 power supply control 3 (r0dh) w r/w rs 1 0 0 0 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 00000 0 dummy1 vrh3 vrh2 vrh1 vrh0 notp1 0 notp1 : notp1 becomes ?0? after power on reset and vlcd 63 voltage becomes programmed eeprom value. when notp1 set to ?1?, setting of vrh3-vrh0 become s valid and voltage of vlcd63 can be adjusted. vrh3-vrh0 : set amplitude magnification of vlcd63. these bits amplify the vlcd63 voltage 1.330 to 2.775 times the vref voltage set by vrh3-vrh0. vrh3 vrh2 vrh1 vrh0 vlcd63 output 0 0 0 0 vref x 1.330 0 0 0 1 vref x 1.450 0 0 1 0 vref x 1.550 0 0 1 1 vref x 1.650 0 1 0 0 vref x 1.750 0 1 0 1 vref x 1.800 0 1 1 0 vref x 1.850 0 1 1 1 stopped 1 0 0 0 vref x 1.900 1 0 0 1 vref x 2.175. 1 0 1 0 vref x 2.325 1 0 1 1 vref x 2.475 1 1 0 0 vref x 2.625 1 1 0 1 vref x 2.700 1 1 1 0 vref x 2.775 1 1 1 1 stopped caution vlcd63 output voltage that is set by vrh [3:0] setting is limited under vcix2 voltage. vref is the internal reference voltage equals to 2.0 v. data sheet s17594ej2v0ds 42 pd161608 13.8 power supply control 4 (r0eh) w r/w rs 1 notp2 dummy2 vcomg vdv4 0 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 vdv3 vdv2 vdv1 vdv0 0000000 notp2 : notp2 becomes ?0? after power on reset and vcom amplitude voltage becomes programmed eeprom value. when notp1 set to ?1?, setting of vdv4-vdv0 becomes valid and voltage of vcom amplitude voltage can be adjusted. vcomg : when vcomg = ?1?, it is possible to set output volt age of vcoml to any level, and the instruction (vdv4- vdv0) becomes available. when vcomg = ?0?, vcoml out put is fixed to hi-z level, vci2 output for vcoml power supply stops, and the instruction (vdv4-vdv0) be comes unavailable. set vcomg according to the sequence of power supply setting flow as it relates with power supply operating sequence. vdv4-vdv0 : set the alternating amplitudes of vcom at the vcom alternating drive. these bits amplify vcom amplitude 0.6 to 1.23 times the vlcd63 voltage. when vcomg = ?0?, the settings become invalid. external voltage at vcomr is referenced when vdv4-vdv0 = ?01111?. vdv4 vdv3 vdv2 vdv1 vdv0 vcom amplitude 0 0 0 0 0 vlcd63 x 0.60 0 0 0 0 1 vlcd63 x 0.63 0 0 0 1 0 vlcd63 x 0.66 : : : : : : step = 0.03 : 0 1 1 0 1 vlcd63 x 0.99 0 1 1 1 0 vlcd63 x 1.02 0 1 1 1 1 reference from external variable resister 1 0 0 0 0 vlcd63 x 1.05 1 0 0 0 1 vlcd63 x 1.08 : : : : : : step = 0.03 : 1 0 1 0 1 vlcd63 x 1.20 1 0 1 1 0 vlcd63 x 1.23 1 0 1 1 1 setting disable 1 1 * * * setting disable remark *: don?t care caution when set to 8-color mode (cm = h), vcoml output voltage is fixed to 0 v and above- mentioned setting is ignored. data sheet s17594ej2v0ds 43 pd161608 13.9 gate scan start position (r0fh) w r/w rs 1 0 0 0 0 0 0 0 0 scn7 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 scn6 scn5 scn4 scn3 scn2 scn1 scn0 scn7-scn0 : set the scanning starting po sition of the gate driver. nec electronics nec electronics g0 g219 g219 g0 g50 1st line of data 1st line of data scn [7:0] = 00000000 scn [7:0] = 00110010 13.10 horizontal porch (r16h) w r/w rs 1 1 1 1 1 0 1 0 1 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 0 0 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 hbp5-hbp0 : set the delay period from falling edge of hsync signal to first valid data. the pixel data exceed 176 and before the first valid data will be treated as dummy data. hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 number of clock cycle of dotclk 0 0 0 0 0 0 8 0 0 0 0 0 1 8 0 0 0 0 1 0 8 0 0 0 0 1 1 8 0 0 0 1 0 0 8 0 0 0 1 0 1 8 0 0 0 1 1 0 8 0 0 0 1 1 1 9 0 0 1 0 0 0 10 : : : : : : : step = 1 : 1 1 1 1 1 0 64 1 1 1 1 1 1 65 data sheet s17594ej2v0ds 44 pd161608 13.11 vertical porch (r17h) w r/w rs 1 0 0 0 0 0 0 0 0 vbp7 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 vbp7-vbp0 : set the delay period from falling edge of vsync to first valid line. the line data within this delay period will be treated as dummy line. vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 nu mber of clock cycle of hsync 0 0 0 0 0 0 0 0 setting disable 0 0 0 0 0 0 0 1 setting disable 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 0 4 0 0 0 0 0 1 0 1 5 : : : : : : : : : step = 1 : 1 1 0 1 1 0 1 1 219 1 1 0 1 1 1 0 0 220 1 1 0 1 1 1 0 1 setting disable 1 1 0 1 1 1 1 * setting disable 1 1 1 * * * * * setting disable remark *: don?t care 13.12 power supply control 5 (r1eh) w r/w rs 1 0 0 0 0 0 0 0 0 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 notp3 dummy3 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 notp3 : notp3 becomes ?0? after power on reset and vcomh voltage becomes programmed eeprom value. when notp3 set to ?1?, setting of vcm5-vcm0 becomes valid and voltage of vcomh can be adjusted. vcm5-vcm0 : set the 262 k-color mode of vcomh voltage if notp 3 = ?1?. these bits amplify the vcomh voltage 0.36 to 0.99 times the vlcd63 voltage. vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 vcomh output 0 0 0 0 0 0 vlcd63 x 0.36 0 0 0 0 0 1 vlcd63 x 0.37 0 0 0 0 1 0 vlcd63 x 0.38 0 0 0 0 1 1 vlcd63 x 0.39 : : : : : : : step = 0.01 : 1 1 1 1 1 0 vlcd63 x 0.98 1 1 1 1 1 1 vlcd63 x 0.99 data sheet s17594ej2v0ds 45 pd161608 13.13 software reset (r28h) register can be reset to its por default val ues upon the following sequence are completed. step resister value internal operation 1 r28h 0006 idle 2 r28h 000e initialize register 3 r28h 0000 reset is released. caution all other above settings of r28h ar e reserved. therefor e, please don?t set up. 13.14 gamma control1 to 10 (r30h to r37h, r3ah, r3bh) for more detail, refer to 14. gamma adjustment function . ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 rs r/w 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 0 0 0 w 1 0 0 w 1 reg. r30h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r31h r32h r33h r34h r35h r36h r37h r3ah r3bh notp4 dummy4 pkp12 pkp32 pkp52 prp12 pkn12 pkn02 pkn22 pkn42 pkn41 pkn40 pkn21 pkn20 pkn01 pkn00 pkn32 pkn52 prn12 prn02 prn01 prn00 vrp12 vrp14 vrp13 vrn12 vrn14 vrn13 vrn11 vrn10 vrn00 vrn01 vrn02 vrn03 vrp11 vrp10 vrp00 vrp01 vrp02 vrp03 prn11 prn10 pkn51 pkn50 pkn31 pkn30 pkn11 pkn10 prp11 prp10 prp02 prp01 prp00 pkp51 pkp50 pkp31 pkp30 pkp02 pkp22 pkp42 pkp41 pkp40 pkp21 pkp20 pkp01 pkp00 pkp11 pkp10 notp4 : notp4 becomes ?0? after power on reset and gamm a curve setting (r30h-r37h, r3ah, r3bh) becomes programmed eeprom value. when notp4 set to ?1?, setting of r30h-r37h, r3ah, r3bh become valid and voltage of each gamma curve can be adjusted. pkp52-pkp00 : micro-adjustment register fo r the positive polarity output prp12-prp00 : gray-scale adjustment register for the positive polarity output pkn52-pkn00 : micro-adjustment register fo r the negative polarity output prn12-prn00 : gray-scale adjustment register for the negative polarity output vrp14-vrp10 : amplitude adjustment register for the positive polarity output vrp03-vrp00 : reference adjustment register for the positive polarity output vrn14-vrn10 : amplitude adjustment register for the negative polarity output vrn03-vrn00 : reference adjustment register for the negative polarity output data sheet s17594ej2v0ds 46 pd161608 13.15 power supply control 6 (r52h) w r/w rs 1 dcsel vghon vcix2on ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 vci2on vglon vl63on vcomon dcon 00 111100 dcsel : this flag selects power set-up mode as follows. dcsel = 0: auto sequence mode off, vg hon/vcix2on/vci2on/vglon/vl63on are valid. dcsel = 1: auto sequence mode vghon : when dcsel=0, this flag is valid. vgh power supply circuit is control as follows. vghon = 0: halt vghon = 1: operate vcix2on : when dcsel = 0, this flag is valid. vcix2 power supply circuit is control as follows. vcix2on = 0: halt vcix2on = 1: operate vci2on : when dcsel = 0, this flag is valid. se t the output voltage of vcix2 as follows. vcix2on = 0: vc [3:0] (r11h) is valid vcix2on = 1: vc [3:0] (r11h) setting value ?1 v vglon : when dcsel = 0, this flag is valid. vgl power supply circuit is control as follows. vglon = 0: halt vglon = 1: operate vl63on : when dcsel = 0, this flag is valid. vlcd63 regulator circuit is control as follows. vl63on = 0: halt vl63on = 1: operate vcomon : when dcsel = 0, this flag is valid. regulator circuit for common output is control as follows. vcomon = 0: halt vcomon = 1: operate cautions 1. the case to set this re gister, don?t change the ib7-ib0?s valu e above-mentioned register value. 2. above- mentioned r52h setting is not used except ?eerom data write sequence?. data sheet s17594ej2v0ds 47 pd161608 13.16 vgh off setting (r54h) w r/w rs 1 0 0 0 ib15 ib14 ib13 vghoff ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 0 0000 000000 0 vghoff : this flag control vgh output as follows. vghoff = 0: normal operation vghoff = 1: vgh halt (vcix2 voltage level is output). 13.17 eeprom mode setting (r60h) w r/w rs 1 0 0 0 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 000000000 ep_ read ep_ pwr ep_ write 0 ep_read, ep_write : read/write setting mode select of eeprom. eepr om setting mode is select by these bits as follow table. for mo re detail, refer to 22. eeprom access . ep_read ep_write eeprom setting mode 0 0 normal operation 0 1 eeprom write setting 1 0 eeprom read setting 1 1 setting disable ep_pwr : select power supply mode during ?eeprom write? as follow table. for more detail, refer to 22. eeprom access . ep_pwr power supply mode 0 external power supply mode (supply to vgh/vgl pins by externally) 1 internal power supply mode data sheet s17594ej2v0ds 48 pd161608 13.18 eeprom operation control (r61h) w r/w rs 1 0 0 0 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 000000000 ie2op c2 ie2op c1 ie2op c0 0 ie2opc2-ie2opc0 : control the access to eeprom as follow table. for more detail, refer to 22. eeprom access . ie2opc2 ie2opc1 ie2opc0 eeprom access setting 0 0 0 nop (non operation) 0 0 1 write (eeprom write) 0 1 0 reserved 0 1 1 reserved 1 0 0 erase 1 0 1 nop 1 1 0 read (eeprom read) 1 1 1 reserved 13.19 eeprom monitor (r70h to r7dh) register no. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 70h r 1 parity 0 0 dummy5 dummy1 vrh3 vrh2 vrh1 vrh0 71h r 1 parity dummy6 dummy2 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 72h r 1 parity dummy7 dummy3 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 73h r 1 parity dummy8 dummy4 pkp12 pkp11 pkp10 pkp02 pkp01 pkp00 74h r 1 parity 0 pkp32 pkp31 pkp30 0 pkp22 pkp21 pkp20 75h r 1 parity 0 pkp52 pkp51 pkp50 0 pkp42 pkp41 pkp40 76h r 1 parity 0 prp12 prp11 prp10 0 prp02 prp01 prp00 77h r 1 parity 0 pkn12 pkn11 pkn10 0 pkn02 pkn01 pkn00 78h r 1 parity 0 pkn32 pkn31 pkn30 0 pkn22 pkn21 pkn20 79h r 1 parity 0 pkn52 pkn51 pkn50 0 pkn42 pkn41 pkn40 7ah r 1 parity 0 prn12 prn11 prn10 0 prn02 prn01 prn00 7bh r 1 parity vrp12 vrp11 vrp10 0 vrp03 vrp02 vrp01 vrp00 7ch r 1 parity vrn12 vrn11 vrn10 0 vrn03 vrn02 vrn01 vrn00 7dh r 1 there are no actual registers. when these registers are read, value is '0'. parity 0 0 vrn14 vrn13 0 0 vrp14 vrp13 r70h-r7dh is a register which moni tors content written to eeprom. parity bit of ib8 bit of instruction bit becomes 0 befor e written to eeprom. once it is written to eeprom, these registers calculate parity. data sheet s17594ej2v0ds 49 pd161608 14. gamma adjustment function the pd161608 provides the gamma adjustment function to display 262,144 colors simultaneously. the gamma adjustment executed by the gray-scale adjus tment register and the micro-adjustment register that determines 8 gray-scale levels. furthermore, since the gray-scale adjustment register and the micro-adjustment register hav e the positive polarities and negative polarities, adjust them to match lcd panel respectively. figure 14 ? 1. gray-scale control pkp02 pkn02 prn02 vrn02 vrn12 vrn13 vrn14 vrn11 vrn10 vrn01 vrn03 vrn00 prn12 prn11 prn10 prn01 prn00 pkn12 pkn11 pkn10 pkn22 pkn21 pkn20 pkn32 pkn31 pkn30 pkn42 pkn41 pkn40 pkn52 pkn51 pkn50 pkn01 pkn00 prp02 vrp02 vrp12 vrp13 vrp14 vrp11 vrp10 vrp03 vrp01 vrp00 prp12 prp11 prp10 prp01 prp00 pkp12 pkp11 pkp10 pkp22 positive polarity register negative polarity register pkp21 pkp20 pkp32 pkp31 pkp30 pkp42 pkp41 pkp40 pkp52 pkp51 pkp50 pkp01 pkp00 r1 r0 r2 r3 r4 r5 g5 b5 b4 b3 b2 b1 b0 g4 g3 g2 g1 g0 8 gray-scale amplifier 6 r data sheet s17594ej2v0ds 50 pd161608 15. structure of gray-scale amplifier the structure of gray-scale amplifier is shown as belo w. 8-voltage-level (vinp0/vinp7-vinn0/vinn7) between vlcd63 and exvr are determined by the gray-scale adjustment register and the micro adjustment register. each level is split into 8 levels again by the internal ladder resistor network. as a result, gray-scale amplifier generates 64 voltage levels ranging from v0-v63 and outputs one of 64 levels. a gamma ad justment executed by the lcd panel respectively. figure 15 ? 1. structure of gray-scale amplifier vlcd63 ladder resistor gradient adjustment amplitude adjustment micro adjustment register (6 x 3-bit) exvr prp/n0, prp/n1 pkp/n0 pkp/n1 pkp/n2 pkp/n3 pkp/n4 pkp/n5 vrp/n0 vrp/n1 vinp0 /vinn0 vinp1 /vinn1 vinp2 /vinn2 vinp3 /vinn3 vinp4 /vinn4 vinp5 /vinn5 vinp6 /vinn6 vinp7 /vinn7 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 8 to 1 selector 3 3 3 3 3 3 3 3 4 5 v 0 v 1 v 2 v 3 v 8 v 9 v 20 v 21 v 43 v 44 v 55 v 56 v 57 v 62 v 63 gray-scale amplifier data sheet s17594ej2v0ds 51 pd161608 figure 15 ? 2. structure of resistor ladder network/8 to 1 selector 8 to 1 sel rp1 kvp1 kvp0 rp0 pkp0 [2: 0] 5r 4r kvp2 rp2 kvp3 rp3 kvp4 rp4 kvp5 rp5 kvp6 rp6 kvp7 rp7 kvp8 vinp1 vinp0 vinp7 8 to 1 sel rp8 kvp9 pkp1 [2: 0] vrhp 0 to 28r kvp10 rp9 kvp11 rp10 kvp12 rp11 kvp13 rp12 kvp14 rp13 kvp15 rp14 kvp16 prp0 [2: 0] vinp2 8 to 1 sel rp16 kvp17 rp15 pkp2 [2: 0] 5r kvp18 rp17 kvp19 rp18 kvp20 rp19 kvp21 rp20 kvp22 rp21 kvp23 rp22 kvp24 vinp3 8 to 1 sel rp24 kvp25 rp23 pkp3 [2: 0] 16r kvp26 rp25 kvp27 rp26 kvp28 rp27 kvp29 rp28 kvp30 rp29 kvp31 rp30 kvp32 vinp4 8 to 1 sel rp32 kvp33 rp31 pkp4 [2: 0] 5r kvp49 rp46 5r rp47 8r kvp34 rp33 kvp35 rp34 kvp36 rp35 kvp37 rp36 kvp38 rp37 kvp39 rp38 kvp40 vinp5 8 to 1 sel rp39 kvp41 pkp5 [2: 0] kvp42 rp40 kvp43 rp41 kvp44 rp42 kvp45 rp43 kvp46 rp44 kvp47 rp45 kvp48 vinp6 1r 1r 1r 1r 4r vrp0 0 to 30r vrp0 [3: 0] vrlp 0 to 28r prp1 [2: 0] vrp1 [4: 0] vrp 0 to 31r 8 to 1 sel rn1 kvn1 kvp0 rn0 pkn0 [2: 0] 5r 4r kvn2 rn2 kvn3 rn3 kvn4 rn4 kvn5 rn5 kvn6 rn6 kvn7 rn7 kvn8 vinn1 vinn0 vinn7 8 to 1 sel rn8 kvn9 pkn1 [2: 0] vrhn 0 to 28r kvn10 rn9 kvn11 rn10 kvn12 rn11 kvn13 rn12 kvn14 rn13 kvn15 rn14 kvn16 prn0 [2: 0] vinn2 8 to 1 sel rn16 kvn17 rn15 pkn2 [2: 0] 5r kvn18 rn17 kvn19 rn18 kvn20 rn19 kvn21 rn20 kvn22 rn21 kvn23 rn22 kvn24 vinn3 8 to 1 sel rn24 kvn25 rn23 pkn3 [2: 0] 16r kvn26 rn25 kvn27 rn26 kvn28 rn27 kvn29 rn28 kvn30 rn29 kvn31 rn30 kvn32 vinn4 8 to 1 sel rn32 kvn33 rn31 pkn4 [2: 0] 5r kvn49 rn46 5r rn47 8r kvn34 rn33 kvn35 rn34 kvn36 rn35 kvn37 rn36 kvn38 rn37 kvn39 rn38 kvn40 vinn5 8 to 1 sel rn39 kvn41 pkn5 [2: 0] kvn42 rn40 kvn43 rn41 kvn44 rn42 kvn45 rn43 kvn46 rn44 kvn47 rn45 kvn48 vinn6 1r 1r 1r 1r 4r vrn0 0 to 30r vrn0 [3: 0] vrln 0 to 28r prn1 [2: 0] vrn1 [4: 0] vrn 0 to 31r vlcd63 exvr data sheet s17594ej2v0ds 52 pd161608 16. gamma adjustment register the gamma adjustment register sets up the gray-scale volt age adjusting to the gamma spec ification of the lcd panel. this register can set positive/neg ative polarities independently. there are 3 ty pes of register groups to adjust gray-scale and oscillation on number of the gray-scale, characteristics of the gray -scale voltage (but, r.g.b. is commonness). following graphics indicate the operation of each adjusting register. figure 16 ? 1. the operation of adjusting register (1) gray-scale adjustment gray-scale number gray-scale voltage gray-scale voltage gray-scale voltage gray-scale voltage gray-scale number gray-scale number gray-scale number (2) reference adjustment (3) amplitude adjustment (4) micro adjustment 16.1 gray-scale adjustment resistor the gray-scale adjustment resistors are used to adjust the gray-scale in the middle of the gray-scale characteristics for the voltage without changing the dynamic range. to accomplis h the adjustment, it controls the variable resistor (vrhp (n)/vrlp (n)) of the ladder resistor for the gray-scale volt age generator. also, there is an independent resistor on the positive/negative polarities in order fo r corresponding to asymmetry drive. 16.2 reference adjustment resistor the reference-adjusting resistor is to adjust reference of the gray-scale voltage. to accomplish the adjustment, it controls the variable resistor (vrp(n) 0) of the ladder resistor for the gray-scale voltage generator located at upper side of the ladder resistor. 16.3 amplitude adjustment resistor the amplitude-adjusting resistor is to adjust amplitude of the gray-scale voltage. to accomplish the adjustment, it controls the variable resistor (vrp(n) 1) of the ladder resistor for the gray-scale voltage generator located at lower side of the ladder resistor (adjust upper side by input vlcd63 level). also, there is an independent resistor on the positive/negative polarities as well as the gray-scale adjusting resistor. 16.4 micro adjustment resistor the micro adjustment resistor is to make subtle adjust ment of the gray-scale voltage level. to accomplish the adjustment, it controls the each reference voltage level by th e 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. also , there is an independent resistor on t he positive/negative pol arities as well as other adjusting resistors. data sheet s17594ej2v0ds 53 pd161608 table 16 ? 1. gamma adjusting register register group positive polarity negative polarity set-up contents prp02 to prp00 prn02 to prn00 variable resistor vrhp(n) gray-scale adjustment prp12 to prp10 prn12 to prn10 variable resistor vrlp(n) reference adjustment vrp03 to vrp00 vrn 03 to vrn00 variable resistor vrp(n)0 amplitude adjustment vrp14 to vrp10 vrn14 to vrn10 variable resistor vrp(n)1 pkp02 to pkp00 pkn02 to pkn00 the voltage of gray-scale number 1 is selected by the 8 to 1 selector pkp12 to pkp10 pkn12 to pkn10 the voltage of gray-scale number 8 is selected by the 8 to 1 selector pkp22 to pkp20 pkn22 to pkn20 the voltage of gray-scale number 20 is selected by the 8 to 1 selector pkp32 to pkp30 pkn32 to pkn30 the voltage of gray-scale number 43 is selected by the 8 to 1 selector pkp42 to pkp40 pkn42 to pkn40 the voltage of gray-scale number 55 is selected by the 8 to 1 selector micro-adjustment pkp52 to pkp50 pkn52 to pkn50 the voltage of gray-scale number 62 is selected by the 8 to 1 selector data sheet s17594ej2v0ds 54 pd161608 17. ladder resistor / 8 to 1 selector the ladder resistor / 8 to 1 selector output s the reference voltage of the gray-scale voltage. there are two ladder resistor networks including variable resistor and the 8 to 1 selector selecting voltage generated by t he ladder resistor network. the gamma resistor controls the variable and 8 to 1 resistor s. also, there is a pin connected to the external volume resistor. and it can compensate the dis persion of length between one panel to another. 17.1 variable resistor there are 3 types of the variable re sistors that is for the gray-scale adj ustment (vrhp(n)/vrlp(n)), for reference adjustment (vrp(n)0), and for the amplit ude adjustment (vrp(n)1). the resistance value is set by the gray-scale adjusting resistor (1), (2), reference adjustment resi stor, and the oscillation-adjusting resistor as below. table 17 ? 1. gray-scale adjustment (1) register value prp(n)0 [2:0] resistance value vrhp(n) 000 0r 001 4r 010 8r 011 12r 100 16r 101 20r 110 24r 111 28r table 17 ? 2. gray-scale adjustment (2) register value prp(n)1 [2:0] resistance value vrlp(n) 000 0r 001 4r 010 8r 011 12r 100 16r 101 20r 110 24r 111 28r table 17 ? 3. reference adjustment register value vrp(n)0 [3:0 ] resistance value vrp(n)0 0000 0r 0001 2r 0010 4r : : step = 1r : 1101 26r 1110 28r 1111 30r data sheet s17594ej2v0ds 55 pd161608 table 17 ? 4. amplitude adjustment register value vrp(n)1 [4:0 ] resistance value vrp(n)1 00000 0r 00001 1r 00010 2r : : step = 1r : 10110 22r 10111 23r 11000 24r : : step = 1r : 11101 29r 11110 30r 11111 31r data sheet s17594ej2v0ds 56 pd161608 18. the 8 to 1 selector by the 8 to 1 selector, one of the voltage levels given by the ladder resistor network and t he micro-adjusting register is selected. the 8 to 1 selector output s one of the six types of reference voltages, the vinp(n)1 to vinp(n)6. following table explains the relationship between the micro-adjusting register and the selecting voltage. table 18 ? 1. relationship between micro-adjusting register and selected voltage selected voltage register value pkp(n) [2:0] vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 000 kvp(n)1 kvp(n)9 kvp(n)17 kvp(n)25 kvp(n)33 kvp(n)41 001 kvp(n)2 kvp(n)10 kvp(n)18 kvp(n)26 kvp(n)34 kvp(n)42 010 kvp(n)3 kvp(n)11 kvp(n)19 kvp(n)27 kvp(n)35 kvp(n)43 011 kvp(n)4 kvp(n)12 kvp(n)20 kvp(n)28 kvp(n)36 kvp(n)44 100 kvp(n)5 kvp(n)13 kvp(n)21 kvp(n)29 kvp(n)37 kvp(n)45 101 kvp(n)6 kvp(n)14 kvp(n)22 kvp(n)30 kvp(n)38 kvp(n)46 110 kvp(n)7 kvp(n)15 kvp(n)23 kvp(n)31 kvp(n)39 kvp(n)47 111 kvp(n)8 kvp(n)16 kvp(n)24 kvp(n)32 kvp(n)40 kvp(n)48 the gray-scale levels are determined by the following formulas listed in the next pages. data sheet s17594ej2v0ds 57 pd161608 table 18 ? 2. gamma adjusting voltage formula (positive polarity) pins formula micro-adjusting register value reference voltage kvp0 vlcd63- v*vrp0/sumrp ? vinp0 kvp1 vlcd63- v*(vrp0+5r)/sumrp pkp02-00 = ?000? kvp2 vlcd63- v*(vrp0+9)/sumrp pkp02-00 = ?001? kvp3 vlcd63- v*(vrp0+13r)/sumrp pkp02-00 = ?010? kvp4 vlcd63- v*(vrp0+17r)/sumrp pkp02-00 = ?011? kvp5 vlcd63- v*(vrp0+21r)/sumrp pkp02-00 = ?100? kvp6 vlcd63- v*(vrp0+25r)/sumrp pkp02-00 = ?101? kvp7 vlcd63- v*(vrp0+29r)/sumrp pkp02-00 = ?110? kvp8 vlcd63- v*(vrp0+33r)/sumrp pkp02-00 = ?111? vinp1 kvp9 vlcd63- v*(vrp0+33r+vrhp)/sumrp pkp12-10 = ?000? kvp10 vlcd63- v*(vrp0+34r+vrhp)/sumrp pkp12-10 = ?001? kvp11 vlcd63- v*(vrp0+35r+vrhp)/sumrp pkp12-10 = ?010? kvp12 vlcd63- v*(vrp0+36r+vrhp)/sumrp pkp12-10 = ?011? kvp13 vlcd63- v*(vrp0+37r+vrhp)/sumrp pkp12-10 = ?100? kvp14 vlcd63- v*(vrp0+38r+vrhp)/sumrp pkp12-10 = ?101? kvp15 vlcd63- v*(vrp0+39r+vrhp)/sumrp pkp12-10 = ?110? kvp16 vlcd63- v*(vrp0+40r+vrhp)/sumrp pkp12-10 = ?111? vinp2 kvp17 vlcd63- v*(vrp0+45r+vrhp)/sumrp pkp22-20 = ?000? kvp18 vlcd63- v*(vrp0+46r+vrhp)/sumrp pkp22-20 = ?001? kvp19 vlcd63- v*(vrp0+47r+vrhp)/sumrp pkp22-20 = ?010? kvp20 vlcd63- v*(vrp0+48r+vrhp)/sumrp pkp22-20 = ?011? kvp21 vlcd63- v*(vrp0+49r+vrhp)/sumrp pkp22-20 = ?100? kvp22 vlcd63- v*(vrp0+50r+vrhp)/sumrp pkp22-20 = ?101? kvp23 vlcd63- v*(vrp0+51r+vrhp)/sumrp pkp22-20 = ?110? kvp24 vlcd63- v*(vrp0+52r+vrhp)/sumrp pkp22-20 = ?111? vinp3 kvp25 vlcd63- v*(vrp0+68r+vrhp)/sumrp pkp32-30 = ?000? kvp26 vlcd63- v*(vrp0+69r+vrhp)/sumrp pkp32-30 = ?001? kvp27 vlcd63- v*(vrp0+70r+vrhp)/sumrp pkp32-30 = ?010? kvp28 vlcd63- v*(vrp0+71r+vrhp)/sumrp pkp32-30 = ?011? kvp29 vlcd63- v*(vrp0+72r+vrhp)/sumrp pkp32-30 = ?100? kvp30 vlcd63- v*(vrp0+73r+vrhp)/sumrp pkp32-30 = ?101? kvp31 vlcd63- v*(vrp0+74r+vrhp)/sumrp pkp32-30 = ?110? kvp32 vlcd63- v*(vrp0+75r+vrhp)/sumrp pkp32-30 = ?111? vinp4 kvp33 vlcd63- v*(vrp0+80r+vrhp)/sumrp pkp42-40 = ?000? kvp34 vlcd63- v*(vrp0+81r+vrhp)/sumrp pkp42-40 = ?001? kvp35 vlcd63- v*(vrp0+82r+vrhp)/sumrp pkp42-40 = ?010? kvp36 vlcd63- v*(vrp0+83r+vrhp)/sumrp pkp42-40 = ?011? kvp37 vlcd63- v*(vrp0+84r+vrhp)/sumrp pkp42-40 = ?100? kvp38 vlcd63- v*(vrp0+85r+vrhp)/sumrp pkp42-40 = ?101? kvp39 vlcd63- v*(vrp0+86r+vrhp)/sumrp pkp42-40 = ?110? kvp40 vlcd63- v*(vrp0+87r+vrhp)/sumrp pkp42-40 = ?111? vinp5 kvp41 vlcd63- v*(vrp0+87r+vrhp+vrlp)/sumrp pkp52-50 = ?000? kvp42 vlcd63- v*(vrp0+91r+vrhp+vrlp)/sumrp pkp52-50 = ?001? kvp43 vlcd63- v*(vrp0+95r+vrhp+vrlp)/sumrp pkp52-50 = ?010? kvp44 vlcd63- v*(vrp0+99r+vrhp+vrlp)/sumrp pkp52-50 = ?011? kvp45 vlcd63- v*(vrp0+103r+vrhp+vrlp)/sumrp pkp52-50 = ?100? kvp46 vlcd63- v*(vrp0+107r+vrhp+vrlp)/sumrp pkp52-50 = ?101? kvp47 vlcd63- v*(vrp0+111r+vrhp+vrlp)/sumrp pkp52-50 = ?110? kvp48 vlcd63- v*(vrp0+115r+vrhp+vrlp)/sumrp pkp52-50 = ?111? vinp6 kvp49 vlcd63- v*(vrp0+120r+vrhp+vrlp)/sumrp ? vinp7 remark sumrp: total of the positive polarity ladder resistance = vrp0 + 128r + vrhp + vrlp + vrp sumrn: total of the negative polarity ladder resistance = vrn0 + 128r + vrhn + vrln + vrn v: potential difference between kv0 and kv49 = vlcd 63*sumrp*sumrn/[sumrp*sumrn+exvr*(sumrp+sumrn)] data sheet s17594ej2v0ds 58 pd161608 table 18 ? 3. gamma voltage formula (positive polarity) gray-scale voltage formula gray-scale voltage formula v0 vinp0 v32 v43+(v20-v43)*(11/23) v1 vinp1 v33 v43+(v20-v43)*(10/23) v2 v8+(v1-v8)*(30/48) v34 v43+(v20-v43)*(9/23) v3 v8+(v1-v8)*(23/48) v35 v43+(v20-v43)*(8/23) v4 v8+(v1-v8)*(16/48) v36 v43+(v20-v43)*(7/23) v5 v8+(v1-v8)*(12/48) v37 v43+(v20-v43)*(6/23) v6 v8+(v1-v8)*(8/48) v38 v43+(v20-v43)*(5/23) v7 v8+(v1-v8)*(4/48) v39 v43+(v20-v43)*(4/23) v8 vinp2 v40 v43+(v20-v43)*(3/23) v9 v20+(v8-v20)*(22/24) v41 v43+(v20-v43)*(2/23) v10 v20+(v8-v20)*(20/24) v42 v43+(v20-v43)*(1/23) v11 v20+(v8-v20)*(18/24) v43 vinp4 v12 v20+(v8-v20)*(16/24) v44 v55+(v43-v55)*(22/24) v13 v20+(v8-v20)*(14/24) v45 v55+(v43-v55)*(20/24) v14 v20+(v8-v20)*(12/24) v46 v55+(v43-v55)*(18/24) v15 v20+(v8-v20)*(10/24) v47 v55+(v43-v55)*(16/24) v16 v20+(v8-v20)*(8/24) v48 v55+(v43-v55)*(14/24) v17 v20+(v8-v20)*(6/24) v49 v55+(v43-v55)*(12/24) v18 v20+(v8-v20)*(4/24) v50 v55+(v43-v55)*(10/24) v19 v20+(v8-v20)*(2/24) v51 v55+(v43-v55)*(8/24) v20 vinp3 v52 v55+(v43-v55)*(6/24) v21 v43+(v20-v43)*(22/23) v53 v55+(v43-v55)*(4/24) v22 v43+(v20-v43)*(21/23) v54 v55+(v43-v55)*(2/24) v23 v43+(v20-v43)*(20/23) v55 vinp5 v24 v43+(v20-v43)*(19/23) v56 v62+(v55-v62)*(44/48) v25 v43+(v20-v43)*(18/23) v57 v62+(v55-v62)*(40/48) v26 v43+(v20-v43)*(17/23) v58 v62+(v55-v62)*(36/48) v27 v43+(v20-v43)*(16/23) v59 v62+(v55-v62)*(32/48) v28 v43+(v20-v43)*(15/23) v60 v62+(v55-v62)*(25/48) v29 v43+(v20-v43)*(14/23) v61 v62+(v55-v62)*(18/48) v30 v43+(v20-v43)*(13/23) v62 vinp6 v31 v43+(v20-v43)*(12/23) v63 vinp7 data sheet s17594ej2v0ds 59 pd161608 table 18 ? 4. gamma adjusting voltage formula (negative polarity) pins formula micro-adjusting register value reference voltage kvn0 vlcd63- v*vrn0/sumrn ? vinn0 kvn1 vlcd63- v*(vrn0+5r)/sumrn pkn02-00 = ?000? kvn2 vlcd63- v*(vrn0+9)/sumrn pkn02-00 = ?001? kvn3 vlcd63- v*(vrn0+13r)/sumrn pkn02-00 = ?010? kvn4 vlcd63- v*(vrn0+17r)/sumrn pkn02-00 = ?011? kvn5 vlcd63- v*(vrn0+21r)/sumrn pkn02-00 = ?100? kvn6 vlcd63- v*(vrn0+25r)/sumrn pkn02-00 = ?101? kvn7 vlcd63- v*(vrn0+29r)/sumrn pkn02-00 = ?110? kvn8 vlcd63- v*(vrn0+33r)/sumrn pkn02-00 = ?111? vinn1 kvn9 vlcd63- v*(vrn0+33r+vrhn)/sumrn pkn12-10 = ?000? kvn10 vlcd63- v*(vrn0+34r+vrhn)/sumrn pkn12-10 = ?001? kvn11 vlcd63- v*(vrn0+35r+vrhn)/sumrn pkn12-10 = ?010? kvn12 vlcd63- v*(vrn0+36r+vrhn)/sumrn pkn12-10 = ?011? kvn13 vlcd63- v*(vrn0+37r+vrhn)/sumrn pkn12-10 = ?100? kvn14 vlcd63- v*(vrn0+38r+vrhn)/sumrn pkn12-10 = ?101? kvn15 vlcd63- v*(vrn0+39r+vrhn)/sumrn pkn12-10 = ?110? kvn16 vlcd63- v*(vrn0+40r+vrhn)/sumrn pkn12-10 = ?111? vinn2 kvn17 vlcd63- v*(vrn0+45r+vrhn)/sumrn pkn22-20 = ?000? kvn18 vlcd63- v*(vrn0+46r+vrhn)/sumrn pkn22-20 = ?001? kvn19 vlcd63- v*(vrn0+47r+vrhn)/sumrn pkn22-20 = ?010? kvn20 vlcd63- v*(vrn0+48r+vrhn)/sumrn pkn22-20 = ?011? kvn21 vlcd63- v*(vrn0+49r+vrhn)/sumrn pkn22-20 = ?100? kvn22 vlcd63- v*(vrn0+50r+vrhn)/sumrn pkn22-20 = ?101? kvn23 vlcd63- v*(vrn0+51r+vrhn)/sumrn pkn22-20 = ?110? kvn24 vlcd63- v*(vrn0+52r+vrhn)/sumrn pkn22-20 = ?111? vinn3 kvn25 vlcd63- v*(vrn0+68r+vrhn)/sumrn pkn32-30 = ?000? kvn26 vlcd63- v*(vrn0+69r+vrhn)/sumrn pkn32-30 = ?001? kvn27 vlcd63- v*(vrn0+70r+vrhn)/sumrn pkn32-30 = ?010? kvn28 vlcd63- v*(vrn0+71r+vrhn)/sumrn pkn32-30 = ?011? kvn29 vlcd63- v*(vrn0+72r+vrhn)/sumrn pkn32-30 = ?100? kvn30 vlcd63- v*(vrn0+73r+vrhn)/sumrn pkn32-30 = ?101? kvn31 vlcd63- v*(vrn0+74r+vrhn)/sumrn pkn32-30 = ?110? kvn32 vlcd63- v*(vrn0+75r+vrhn)/sumrn pkn32-30 = ?111? vinn4 kvn33 vlcd63- v*(vrn0+80r+vrhn)/sumrn pkn42-40 = ?000? kvn34 vlcd63- v*(vrn0+81r+vrhn)/sumrn pkn42-40 = ?001? kvn35 vlcd63- v*(vrn0+82r+vrhn)/sumrn pkn42-40 = ?010? kvn36 vlcd63- v*(vrn0+83r+vrhn)/sumrn pkn42-40 = ?011? kvn37 vlcd63- v*(vrn0+84r+vrhn)/sumrn pkn42-40 = ?100? kvn38 vlcd63- v*(vrn0+85r+vrhn)/sumrn pkn42-40 = ?101? kvn39 vlcd63- v*(vrn0+86r+vrhn)/sumrn pkn42-40 = ?110? kvn40 vlcd63- v*(vrn0+87r+vrhn)/sumrn pkn42-40 = ?111? vinn5 kvn41 vlcd63- v*(vrn0+87r+vrhn+vrlp)/sumrn pkn52-50 = ?000? kvn42 vlcd63- v*(vrn0+91r+vrhn+vrlp)/sumrn pkn52-50 = ?001? kvn43 vlcd63- v*(vrn0+95r+vrhn+vrlp)/sumrn pkn52-50 = ?010? kvn44 vlcd63- v*(vrn0+99r+vrhn+vrlp)/sumrn pkn52-50 = ?011? kvn45 vlcd63- v*(vrn0+103r+vrhn+vrlp)/sumrn pkn52-50 = ?100? kvn46 vlcd63- v*(vrn0+107r+vrhn+vrlp)/sumrn pkn52-50 = ?101? kvn47 vlcd63- v*(vrn0+111r+vrhn+vrlp)/sumrn pkn52-50 = ?110? kvn48 vlcd63- v*(vrn0+115r+vrhn+vrlp)/sumrn pkn52-50 = ?111? vinn6 kvn49 vlcd63- v*(vrn0+120r+vrhn+vrlp)/sumrn ? vinn7 remark sumrp: total of the positive polarity ladder re sistance = vrp0 + 128r + vrhp + vrlp + vrp1 sumrn: total of the negative pol arity ladder resistance = vrn0 + 128r + vrhn + vrln + vrn1 v: potential difference between kv0 and kv49 = vlcd 63*sumrp*sumrn/[sumrp*sumrn+exvr*(sumrp+sumrn)] data sheet s17594ej2v0ds 60 pd161608 table 18 ? 5. gamma voltage formula (negative polarity) gray-scale voltage formula gray-scale voltage formula v0 vinn0 v32 v43+(v20-v43)*(11/23) v1 vinn1 v33 v43+(v20-v43)*(10/23) v2 v8+(v1-v8)*(30/48) v34 v43+(v20-v43)*(9/23) v3 v8+(v1-v8)*(23/48) v35 v43+(v20-v43)*(8/23) v4 v8+(v1-v8)*(16/48) v36 v43+(v20-v43)*(7/23) v5 v8+(v1-v8)*(12/48) v37 v43+(v20-v43)*(6/23) v6 v8+(v1-v8)*(8/48) v38 v43+(v20-v43)*(5/23) v7 v8+(v1-v8)*(4/48) v39 v43+(v20-v43)*(4/23) v8 vinn2 v40 v43+(v20-v43)*(3/23) v9 v20+(v8-v20)*(22/24) v41 v43+(v20-v43)*(2/23) v10 v20+(v8-v20)*(20/24) v42 v43+(v20-v43)*(1/23) v11 v20+(v8-v20)*(18/24) v43 vinn4 v12 v20+(v8-v20)*(16/24) v44 v55+(v43-v55)*(22/24) v13 v20+(v8-v20)*(14/24) v45 v55+(v43-v55)*(20/24) v14 v20+(v8-v20)*(12/24) v46 v55+(v43-v55)*(18/24) v15 v20+(v8-v20)*(10/24) v47 v55+(v43-v55)*(16/24) v16 v20+(v8-v20)*(8/24) v48 v55+(v43-v55)*(14/24) v17 v20+(v8-v20)*(6/24) v49 v55+(v43-v55)*(12/24) v18 v20+(v8-v20)*(4/24) v50 v55+(v43-v55)*(10/24) v19 v20+(v8-v20)*(2/24) v51 v55+(v43-v55)*(8/24) v20 vinn3 v52 v55+(v43-v55)*(6/24) v21 v43+(v20-v43)*(22/23) v53 v55+(v43-v55)*(4/24) v22 v43+(v20-v43)*(21/23) v54 v55+(v43-v55)*(2/24) v23 v43+(v20-v43)*(20/23) v55 vinn5 v24 v43+(v20-v43)*(19/23) v56 v62+(v55-v62)*(44/48) v25 v43+(v20-v43)*(18/23) v57 v62+(v55-v62)*(40/48) v26 v43+(v20-v43)*(17/23) v58 v62+(v55-v62)*(36/48) v27 v43+(v20-v43)*(16/23) v59 v62+(v55-v62)*(32/48) v28 v43+(v20-v43)*(15/23) v60 v62+(v55-v62)*(25/48) v29 v43+(v20-v43)*(14/23) v61 v62+(v55-v62)*(18/48) v30 v43+(v20-v43)*(13/23) v62 vinn6 v31 v43+(v20-v43)*(12/23) v63 vinn7 data sheet s17594ej2v0ds 61 pd161608 figure 18 ? 1. relationship between input data and output voltage v0 positive polarity (rev = 1) negative polarity (rev = 0) v63 000000 input data output voltage level 111111 figure 18 ? 2. relationship between source output and v comout sn positive polarity negative polarity v comout data sheet s17594ej2v0ds 62 pd161608 19. the 8-color display mode the pd161608 builds in 8-color display mode. displaying the gray-scale levels in 8-color display mode, gray-scale amplifier and driver amplifier are halt. so t hat it attempts to lower power consumption. figure 19 ? 1. 8-color display control msb 18-bit rgb data lsb r g b lcd v0 r g b r05 g05 b05 b04 b03 b02 b01 b00 g04 g03 g02 g01 g00 r04 r03 r02 r01 r00 msb msb msb vlcd63 binary driver binary driver binary driver data sheet s17594ej2v0ds 63 pd161608 20. n-raster-row reversed ac driver the pd161608 supports not only the lcd reversed ac drive in a one-frame unit but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 128 raster-rows. when a problem affecting display quality occurs, the n-raster-row reversed ac drive can improve the quality. determine the number of the raster-rows n (nw bit set value + 1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-row is reduced, the lcd alternating frequency becomes high. because of this, the charge or dischar ge current is increased in the lcd cells. figure 20 ? 1. example of an ac signal under n-raster-row reversed ac drive 1 2 3 4 219 219 220 220 224 224 1234 1 2 5 1 frame period vertical blank period vertical blank period 1 frame period 1-line inversion (b/c = 1, eor = 1, nw6 to nw0 = 0, 220 gate line display) data sheet s17594ej2v0ds 64 pd161608 21. ac timing following diagram indicates the ac timing on the each ac drive method. after every 1 drawing, the ac timing is occurred on the reversed frame ac drive. after the ac timi ng, the blank (all outputs from the gate: vgl output) in 4h period is inserted. when the reversed n-rast er-row is driving, a blank period of the 4h period is inserted after all screens are drawn. figure 21 ? 1. ac timing n-raster row n-raster row n-raster row n-raster row n-raster row n-raster row n-raster row n-raster row ac ac ac ac ac ac ac ac ac ac frame inversion (b/c = 0) back porch (3 line) frame 1 1 frame period 1 frame period back porch (3 line) front porch (1 line) front porch (1 line) n-line inversion (b/c = 1) data sheet s17594ej2v0ds 65 pd161608 22. eeprom access the pd161608 builds in eeprom for storing the inter nal register setting as following table. and pd161608 can use the this eeprom setting value as def ault value, when set each notp1 (r 0dh), notp2 (r0eh), notp3 (r1eh), notp4 (r30h) bits to ?0?. in addition, eeprom built in the pd161608 has a possibility that saved data may disappear, by irradiating uv light. therefore, in case you perform uv i rradiation especially at a mounting proce ss, be careful to cope with shading etc. registers default in the case not to use eeprom note mode1 mode2 r0dh power control 3 0019h 001ah r0eh power control 4 7200h 7000h r1eh power control 5 0069h 0062h r30h gamma control 1 0800h 0800h r31h gamma control 2 0707h 0707h r32h gamma control 3 0406h 0406h r33h gamma control 4 0000h 0100h r34h gamma control 5 0103h 0103h r35h gamma control 6 0000h 0000h r36h gamma control 7 0707h 0707h r37h gamma control 8 0000h 0001h r3ah gamma control 9 0404h 1e00h r3bh gamma control 10 0006h 000fh note the case not to write any data eeprom eac h notp1 (r0dh), notp2 (r0eh), notp3 (r1eh), notp4 (r30h) bits to ?1?, the pd161608 use above-mentioned table value for each register?s default value. eeprom access outline is shown as following figure. eeprom write compare n < 3 end write complete start sequence sequence (n = 0) rejection yes no ng n + 1 ok end data sheet s17594ej2v0ds 66 pd161608 22.1 eeprom erase/write sequence (internal power supply mode) the pd161608 is able to select the power source for eepro m erase/write. when ep_pwr (r60h) = 1, internal power supply mode is selected. in this mode, pd161608 use the internal dc/dc converter output voltage for eeprom operation. for more detail scheme, refer to following sequence. r60h setting register setting register setting register setting register setting register setting wait >100 ms power on vci 2.7 v v ddio , v dd dcsel = 0 dcon = 1 vghon = 1, vcix2on = 1, vci2on = 0 vglon = 1, vl63on = 0, vcomon = 0 r61h write command wait >300 ms start end ep_read = 0 ep_write = 1 ep_pwr = 1 adjustment value setting dcon = 0 r52h setting compare sequence lcd module check r52h setting data sheet s17594ej2v0ds 67 pd161608 22.2 eeprom compare sequence (comp) the pd161608 has the register (r 70h-r7dh) which carries out the monitor of the contents of the eeprom. by the following sequences, read the contents of r70h-r7dh and compare by comparing with the data which write. correspondence of r70h-r7dh is shown in 13.19 eeprom monitor (r70h to r7dh) . for more detail scheme, refer to following sequence. power on vci dotclk v ddio , v dd start ng ok end r70h to r7dh read compare retry or reject data sheet s17594ej2v0ds 68 pd161608 22.3 initial status before eeprom write serial register map mode1 mode2 r0d h power control (3)0000000000notp1dummy1vrh3vrh2vrh1vrh00019h 001ah r0eh power control ( 4 ) notp2 dumm y 2vcomgvdv4vdv3vdv2vdv1vdv0000000007200h 7000 h r1eh power control ( 5 ) 00000000notp3dumm y 3 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 0069h 0062 h r30 h r-control ( 1 ) 000notp4dumm y 4pkp12pkp11pkp1000000pkp02pkp01pkp000800h 0800 h r31 h r-control (2) 00000pkp32pkp31pkp3000000pkp22pkp21pkp200707h 0707 h r32 h r-control (3) 00000pkp52pkp51pkp5000000pkp42pkp41pkp400406h 0406 h r33 h r-control ( 4 ) 00000prp12prp11prp1000000prp02prp01prp000000h 0100 h r34 h r-control ( 5 ) 00000pkn12pkn11pkn1000000pkn02pkn01pkn000103h 0103 h r35 h r-control ( 6 ) 00000pkn32pkn31pkn3000000pkn22pkn21pkn200000h 0000 h r36 h r-control (7) 00000pkn52pkn51pkn5000000pkn42pkn41pkn400707h 0707 h r37 h r-control ( 8 ) 00000prn12prn11prn1000000prn02prn01prn000000h 0001 h r3ah r-control ( 9 ) 000vrp14vrp13vrp12vrp11vrp100000vrp03vrp02vrp01vrp000404h1e00h r3bhr-control (10) 000vrn14vrn13vrn12vrn11vrn100000vrn03vrn02vrn01vrn000006h 000fh register address register name d15 d14 d13 d5 d9 d8 d7 d6 d12 d11 d10 value d1 d0 d4 d3 d2 eeprom map value mode1 mode2 r00h power control (3) 1111111111ffh1ffh r01h power control (4) 1111111111ffh1ffh r02h power control (5) 1111111111ffh1ffh r03h r-control (1) 1111111111ffh1ffh r04h r-control (2) 1111111111ffh1ffh r05h r-control (3) 1111111111ffh1ffh r06h r-control (4) 1111111111ffh1ffh r07h r-control (5) 1111111111ffh1ffh r08h r-control (6) 1111111111ffh1ffh r09h r-control (7) 1111111111ffh1ffh r0ah r-control (8) 1111111111ffh1ffh r0bh r-control (9) 1111111111ffh1ffh r0ch r-control (10) 1111111111ffh1ffh r0dh r-control (9, 10) 1111111111ffh1ffh d2 d1 d0 d4 d3 d5 d6 eeprom address register name d8 (parity) d7 eeprom monitor register map value mode1 mode2 r70h power control ( 3 ) 000dumm y5 dumm y 1vrh [ 3 ] vrh [ 2 ] vrh [ 1 ] vrh [ 0 ] 0009h 000ah r71h power control ( 4 ) 0dumm y 6dumm y 2vcomg vdv [ 4 ] vdv [ 3 ] vdv [ 2 ] vdv [ 1 ] vdv [ 0 ] 0032h 0030h r72h power control ( 5 ) 0dumm y 7dumm y 3vcm [ 5 ] vcm [ 4 ] vcm [ 3 ] vcm [ 2 ] vcm [ 1 ] vcm [ 0 ] 0029h 0022h r73h r-control ( 1 ) 0dumm y 8dumm y 4pkp1 [ 2 ] pkp1 [ 1 ] pkp1 [ 0 ] pkp0 [ 2 ] pkp0 [ 1 ] pkp0 [ 0 ] 0000h 0000h r74h r-control ( 2 ) 0 0 pkp3 [ 2 ] pkp3 [ 1 ] pkp3 [ 0 ] 0 pkp2 [ 2 ] pkp2 [ 1 ] pkp2 [ 0 ] 0077h 0077h r75h r-control ( 3 ) 0 0 pkp5 [ 2 ] pkp5 [ 1 ] pkp5 [ 0 ] 0 pkp4 [ 2 ] pkp4 [ 1 ] pkp4 [ 0 ] 0046h 0046h r76h r-control ( 4 ) 0 0 prp1 [ 2 ] prp1 [ 1 ] prp1 [ 0 ] 0prp0 [ 2 ] prp0 [ 1 ] prp0 [ 0 ] 0000h 0010h r77h r-control ( 5 ) 0 0 pkn1 [ 2 ] pkn1 [ 1 ] pkn1 [ 0 ] 0 pkn0 [ 2 ] pkn0 [ 1 ] pkn0 [ 0 ] 0013h 0013h r78h r-control ( 6 ) 0 0 pkn3 [ 2 ] pkn3 [ 1 ] pkn3 [ 0 ] 0 pkn2 [ 2 ] pkn2 [ 1 ] pkn2 [ 0 ] 0000h 0000h r79h r-control ( 7 ) 0 0 pkn5 [ 2 ] pkn5 [ 1 ] pkn5 [ 0 ] 0 pkn4 [ 2 ] pkn4 [ 1 ] pkn4 [ 0 ] 0077h 0077h r7ah r-control ( 8 ) 0 0 prn1 [ 2 ] prn1 [ 1 ] prn1 [ 0 ] 0 prn0 [ 2 ] prn0 [ 1 ] prn0 [ 0 ] 0000h 0001h r7bh r-control ( 9 ) 0vrp1 [ 2 ] vrp1 [ 1 ] vrp1 [ 0 ] 0vrp0 [ 3 ] vrp0 [ 2 ] vrp0 [ 1 ] vrp0 [ 0 ] 0084h 00c0h r7ch r-control ( 10 ) 0 vrn1 [ 2 ] vrn1 [ 1 ] vrn1 [ 0 ] 0vrn0 [ 3 ] vrn0 [ 2 ] vrn0 [ 1 ] vrn0 [ 0 ] 0006h 000fh r7dh r-control ( 9, 10 ) 0 0 0 vrn1[4] vrn1[3] 0 0 vrp1[4] vrp1[3] 0000h 0003h there are no actual registers. when there registers are read, value is '0'. d13 register address register name d15 d14 d12 d11 d10 d9 d8 (parity) d7 d6 d1 d0 d5 d4 d3 d2 data sheet s17594ej2v0ds 69 pd161608 22.4 example of after eeprom write status the example that r1eh (power control 5) r egister is set by the customer is shown below. serial register map r1eh is set by the customer. mode1 mode2 r0dh power control ( 3 ) 0000000000notp1dumm y 1 vrh3 vrh2 vrh1 vrh0 0019h 001ah r0eh power control ( 4 ) notp2 dumm y 2vcomgvdv4vdv3vdv2vdv1vdv000000000 7200h 7000h r1eh power control (5 ) 00000000notp3dummy3vcm5vcm4vcm3vcm2vcm1vcm0* * r30h r-control (1 ) 0 0 0 notp4 dummy4 pkp12 pkp11 pkp10 0 0 0 0 0 pkp02 pkp01 pkp00 0800h 0800h r31h r-control (2 ) 0 0 0 0 0 pkp32 pkp31 pkp30 0 0 0 0 0 pkp22 pkp21 pkp20 0707h 0707h r32h r-control (3 ) 0 0 0 0 0 pkp52 pkp51 pkp50 0 0 0 0 0 pkp42 pkp41 pkp40 0406h 0406h r33h r-control (4 ) 0 0 0 0 0 prp12 prp11 prp10 0 0 0 0 0 prp02 prp01 prp00 0000h 0100h r34h r-control (5 ) 0 0 0 0 0 pkn12 pkn11 pkn10 0 0 0 0 0 pkn02 pkn01 pkn00 0103h 0103h r35h r-control ( 6 ) 0 0 0 0 0 pkn32 pkn31 pkn30 0 0 0 0 0 pkn22 pkn21 pkn20 0000h 0000h r36h r-control ( 7 ) 0 0 0 0 0 pkn52 pkn51 pkn50 0 0 0 0 0 pkn42 pkn41 pkn40 0707h 0707h r37h r-control ( 8 ) 0 0 0 0 0 prn12 prn11 prn10 0 0 0 0 0 prn02 prn01 prn00 0000h 0001h r3ah r-control ( 9 ) 0 0 0 vrp14 vrp13 vrp12 vrp11 vrp10 0 0 0 0 vrp03 vrp02 vrp01 vrp00 0404h 1e00h r3bh r-control (10) 0 0 0 vrn14 vrn13 vrn12 vrn11 vrn10 0 0 0 0 vrn03 vrn02 vrn01 vrn00 0006h 000fh register address register name d15 d14 d13 d5 d9 d8 d7 d6 d12 d11 d10 value d1 d0 d4 d3 d2 eeprom map once eeprom write command is executed, all register value are copied to eeprom. and added calculated parity bits. value mode1 mode2 r00h power control (3) x 0 0 dummy5 dummy1 vrh[3] vrh[2] vrh[1] vrh[0] 119h 11ah r01h power control (4) x dummy6 dummy2 vcomg vdv[4] vdv[3] vdv[2] vdv[1] vdv[0] 072h 170h r02h power control (5) x dummy7 dummy3 vcm[5] vcm[4] vcm[3] vcm[2] vcm[1] vcm[0] * * r03h r-control (1) x dummy8 dummy4 pkp1[2] pkp1[1] pkp1[0] pkp0[2] pkp0[1] pkp0[0] 140h 140h r04h r-control (2) x 0 pkp3[2] pkp3[1] pkp3[0] 0 pkp2[2] pkp2[1] pkp2[0] 077h 077h r05h r-control (3) x 0 pkp5[2] pkp5[1] pkp5[0] 0 pkp4[2] pkp4[1] pkp4[0] 146h 146h r06h r-control (4) x 0 prp1[2] prp1[1] prp1[0] 0 prp0[2] prp0[1] prp0[0] 110h 110h r07h r-control (5) x 0 pkn1[2] pkn1[1] pkn1[0] 0 pkn0[2] pkn0[1] pkn0[0] 113h 113h r08h r-control (6) x 0 pkn3[2] pkn3[1] pkn3[0] 0 pkn2[2] pkn2[1] pkn2[0] 000h 000h r09h r-control (7) x 0 pkn5[2] pkn5[1] pkn5[0] 0 pkn4[2] pkn4[1] pkn4[0] 077h 077h r0ah r-control (8) x 0 prn1[2] prn1[1] prn1[0] 0 prn0[2] prn0[1] prn0[0] 000h 101h r0bh r-control (9) x vrp1[2] vrp1[1] vrp1[0] 0 vrp0[3] vrp0[2] vrp0[1] vrp0[0] 084h 0c0h r0ch r-control (10) x vrn1[2] vrn1[1] vrn1[0] 0 vrn0[3] vrn0[2] vrn0[1] vrn0[0] 006h 00fh r0dh r-control (9, 10) x 0 0 vrn1[4] vrn1[3] 0 0 vrp1[4] vrp1[3] 000h 003h d2 d1 d0 d4 d3 d5 d6 eepro m address register name d 8 (parity) d7 eeprom monitor register map value mode1 mode2 r70h power control ( 3 ) x 00dumm y 5dumm y 1vrh [ 3 ] vrh [ 2 ] vrh [ 1 ] vrh [ 0 ] 0119h 011ah r71h power control ( 4 ) x dumm y 6dumm y 2vcomg vdv [ 4 ] vdv [ 3 ] vdv [ 2 ] vdv [ 1 ] vdv [ 0 ] 0072h 0170h r72h power control ( 5 ) x dumm y 7dumm y 3vcm [ 5 ] vcm [ 4 ] vcm [ 3 ] vcm [ 2 ] vcm [ 1 ] vcm [ 0 ] ** r73h r-control ( 1 ) x dumm y 8dumm y 4 pkp1[2] pkp1[1] pkp1[0] pkp0[2] pkp0[1] pkp0[0] 0140h 0140h r74h r-control ( 2 ) x 0 pkp3[2] pkp3[1] pkp3[0] 0 pkp2[2] pkp2[1] pkp2[0] 0077h 0077h r75h r-control ( 3 ) x 0 pkp5 [ 2 ] pkp5 [ 1 ] pkp5 [ 0 ] 0 pkp4 [ 2 ] pkp4 [ 1 ] pkp4 [ 0 ] 0146h 0146h r76h r-control ( 4 ) x 0prp1 [ 2 ] prp1 [ 1 ] prp1 [ 0 ] 0prp0 [ 2 ] prp0 [ 1 ] prp0 [ 0 ] 0110h 0110h r77h r-control ( 5 ) x 0 pkn1 [ 2 ] pkn1 [ 1 ] pkn1 [ 0 ] 0pkn0 [ 2 ] pkn0 [ 1 ] pkn0 [ 0 ] 0113h 0113h r78h r-control ( 6 ) x 0 pkn3[2] pkn3[1] pkn3[0] 0 pkn2[2] pkn2[1] pkn2[0] 0000h 0000h r79h r-control ( 7 ) x 0 pkn5[2] pkn5[1] pkn5[0] 0 pkn4[2] pkn4[1] pkn4[0] 0077h 0077h r7ah r-control ( 8 ) x 0prn1 [ 2 ] prn1 [ 1 ] prn1 [ 0 ] 0 prn0 [ 2 ] prn0 [ 1 ] prn0 [ 0 ] 0000h 0101h r7bh r-control ( 9 ) x vrp1 [ 2 ] vrp1 [ 1 ] vrp1 [ 0 ] 0vrp0 [ 3 ] vrp0 [ 2 ] vrp0 [ 1 ] vrp0 [ 0 ] 0084h 00c0h r7ch r-control ( 10 ) x vrn1 [ 2 ] vrn1 [ 1 ] vrn1 [ 0 ] 0vrn0 [ 3 ] vrn0 [ 2 ] vrn0 [ 1 ] vrn0 [ 0 ] 0006h 000fh r7dh r-control (9, 10) x 0 0 vrn1[4] vrn1[3] 0 0 vrp1[4] vrp1[3] 0000h 0003h there are no actual registers. when there registers are read, value is '0'. d13 register address register name d15 d14 d12 d11 d10 d9 d8 (parity) d7 d6 d1 d0 d5 d4 d3 d2 data sheet s17594ej2v0ds 70 pd161608 23. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol ratings unit power supply voltage v dd ? 0.5 to +3.6 v power supply voltage v ddio ? 0.5 to +6.0 v power supply voltage vci ? 0.5 to +6.0 v power supply voltage vlcd63 ? 0.5 to +6.0 v power supply voltage vgh ? 0.5 to +20.0 v power supply voltage vgl ? 20.0 to +0.5 v power supply voltage vgh-vgl ? 0.5 to +40.0 v input voltage v i ? 0.5 to v ddio +0.5 v input current i i 10 ma output current i o 10 ma operating ambient temperature t a ? 20 to +70 c storage temperature t stg ? 55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ? 20 to +70 c, v ss = 0 v) parameter symbol min. typ. max. unit power supply voltage v dd 1.6 2.7 v power supply voltage v ddio 1.6 3.3 v power supply voltage vci 2.5 2.8 3.3 v power supply voltage vlcd63 3.6 5.0 5.5 v power supply voltage vgh 10.0 13.75 16.5 v power supply voltage (eeprom write) 10.50 10.75 11.00 v power supply voltage vgl ? 13.75 ? 11.0 ? 7.5 v power supply voltage (eeprom write) ? 11.00 ? 10.75 ? 10.50 v power supply voltage vgh-vgl 17.5 24.75 30.25 v power supply voltage vcix2 5.0 5.5 v input voltage v i1 note 0 v ddio v note power supply system of v dd pin data sheet s17594ej2v0ds 71 pd161608 eeprom rewrite cycle characteristics symbol condition min. typ. max. unit rewrite cycle n w ? ? 5 cycle dc characteristics (v ss = 0 v, t a = ? 20 to +70 c) characteristics symbol condition min. typ. max. unit note regvdd = ?h?, v ddio = 2.7 v 3 a 1 i vddios regvdd = ?l?, v ddio = 3.3 v 10 a 1 leakage current i vcis vci = 3.3 v 5 a 1 comh ? 100 +100 mv ? coml ? 100 +100 mv ? vgh 12.4 13.8 14.0 v 2 vgl vci = 2.775 v, bt [2:0] = 011 ? 14.0 ? 13.8 ? 12.4 v 2 vlcd63 tmb = h (mode1) 4.26 4.35 4.44 v 5 lcd driving voltage vlcd63 ? 2 +2 % ? input high voltage v ih 0.8 x v ddio v ddio v 3 input low voltage v il 0 0.2 x v ddio v 3 output high voltage v oh i oh = ? 100 a v ddio ? 0.5 v ddio v 4 output low voltage v ol i ol = 100 a 0.0 0.5 v 4 input leakage current i il v in = v ss or vci ? 1.0 1.0 a 3 output leakage current i ol v in = v ss or vci ? 3.0 3.0 a 4 regulator output voltage rvdd 1.8 2.0 2.2 v 6 notes 1. t a = 25c 2. display off state 3. applied pins for input voltage: rl, tb, bgr, rev, shut, cm, csb, sql, sdi, spid, dotclk, enable, rr [5:0], gg [5:0], bb [5:0], hsync, vsync, resetb, regvdd 4. applied pin for output voltage: sdo 5. t a = 70c 6. regvdd = l, v dd = v ddio > 2.0 v data sheet s17594ej2v0ds 72 pd161608 dc characteristics for lcd driver output (v ss = 0 v, t a = ? 20 to +70 c) characteristics symbol condition min. typ. max. unit note 1st step-up input voltage vci 2.5 3.3 v ? 1st step-up output efficiency vcix2 i load = 500 a 95 99 ? % ? 2nd step-up input voltage vci 3.4 5.5 v ? 2nd step-up output efficiency vgh i load = 100 a 90 95 ? % ? vgl i load = 100 a 90 95 ? % ? 3rd step-up input voltage vci 2.5 3.3 v ? 3rd step-up output efficiency vci2 i load = 100 a 90 95 - % ? lcd gate driver output on resistance r on vgh = 13.775 v, vgl = ? 13.775 v 2 4 k 1 lcd source driver high-level output current (gradation output) i hog v so = 4.5 v, v sx = 3.5 v ? 50 a 2 lcd source driver low-level output current (gradation output) i log v so = 0.5 v, v sx = 1.5 v 50 a 2 4.2 v v so 20 55 mv 2 0.8 v < v so < 4.2 v 10 30 mv 2 output voltage deviation (mean value) vo v so 0.8 v 20 55 mv 2 lcd source driver output voltage range v so v ss + 0.1 vcix2 ? 0.1 v ? lcd source driver high-level output current (binary output) i hob v so = 5.0 v, v sx = 4.0 v ? 100 a 2 lcd source driver low-level output current (binary output) i lob v so = 0.0 v, v sx = 1.0 v 100 a 2 lcd source driver delay t sd vcix2 = 5.5 v, vlcd63 = 5.0 v 35 s ? current consumption during normal operation i vci no load 2.0 ma 3 notes 1. t a = 70c 2. v sx is the voltage applied to analog output pins s0 to s527. v so is the output voltage of analog output pins s0 to s527. 3. v ddio = v dd = 1.875 v, regvdd = v ss , vci = 2.775 v, cm = l (260-k color), rev = h, rr [5:0] = gg [5:0] = bb [5:0] = 000000, r01h-r03h, r0bh, r0dh-r0fh, r16h, r17h, r1eh , r30h-r37h, r3ah, r3bh are default value. dotclk = 2.64 mhz typ., no load, cx, cy, c1, c2, c3 = 0.1 f data sheet s17594ej2v0ds 73 pd161608 rgb data interface characteristics (t a = ? 20 to +70 o c) characteristics symbol min. typ. max. unit dotclk cycle time t dcyc 361 ? ? ns dotclk pulse width high t dchw 150 ? ? ns dotclk pulse width low t dclw 150 ? ? ns enable setup time t ens 30 ? ? ns enable hold time t enh 30 ? ? ns pd data setup time t pds 40 ? ? ns pd data hold time t pdh 40 ? ? ns figure 23 ? 1. ac characteristics (rgb mode) v ih v ih v il v ih t pds t pdh v il v il v il enable dotclk v il t enh t r t f t dchw t dclw t dcyc rr [5:0] gg [5:0] bb [5:0] rr [5:0] gg [5:0] bb [5:0] rr [5:0] gg [5:0] bb [5:0] t ens v il v ih v ih v ih v ih data sheet s17594ej2v0ds 74 pd161608 clock synchronized serial mode characteristics (t a = ? 20 to +70 o c) characteristics symbol min. typ. max. unit serial clock cycle time (write) t sync 100 ? ? ns serial clock cycle time (read) t sync 300 ? ? ns serial clock rise/fall time t r , t f ? ? 15 ns pulse width high for write t schw 35 ? ? ns pulse width high for read t schr 35 ? ? ns pulse width low for write t sclw 35 ? ? ns pulse width low for read t sclr 235 ? ? ns chip select setup time t css 30 ? ? ns chip select hold time t csh 30 ? ? ns serial input data setup time t sids 30 ? ? ns serial input data hold time t sidh 30 ? ? ns serial output data delay time t sodd ? ? 200 ns serial output data hold time t sodh 5 ? ? ns reset timing characteristics (t a = ? 20 to +70 o c) characteristics symbol min. typ. max. unit reset low pulse width t res 10 ? ? s reset release time t rel 10 ? ? s caution reset low pulse width shorter than 1 s do not make reset. it means undesired short pulse such as glitch, bouncing noise or electrostatic discha rge do not cause irregular system reset. data sheet s17594ej2v0ds 75 pd161608 figure 23 ? 2. ac characteristics (spi mode) vol1 v il v ih v il voh1 vol1 v ih t sids t sidh t sodh sck sdi sdo v il v il v ih v il v il csb transfer start input data output data output data input data v ih v il t sodd t css t csh t r t f t schw c t schr t sclw c t sclr t scyc voh1 v ih v ih v ih transfer end figure 23 ? 3. ac characteristics (reset mode) t res t rel resetb v il v il data sheet s17594ej2v0ds 76 pd161608 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd161608 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of june 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 |
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